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    ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON
    2.
    发明公开
    ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON 审中-公开

    公开(公告)号：US20240088285A1

    公开(公告)日：2024-03-14

    申请号：US18513942

    申请日：2023-11-20

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

    IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/66

    CPC分类号： H01L29/7786 ,  H01L21/0262 ,  H01L29/66462

    摘要： Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

    Rough buffer layer for group III-V devices on silicon
    4.
    发明授权
    Rough buffer layer for group III-V devices on silicon 有权

    公开(公告)号：US11862720B2

    公开(公告)日：2024-01-02

    申请号：US17867877

    申请日：2022-07-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

    IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L29/66

    CPC分类号： H01L29/7786 ,  H01L21/0262 ,  H01L29/66462

    摘要： Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

    METHOD FOR FORMING SOI SUBSTRATE
    6.
    发明申请
    METHOD FOR FORMING SOI SUBSTRATE 有权

    公开(公告)号：US20230062601A1

    公开(公告)日：2023-03-02

    申请号：US17460290

    申请日：2021-08-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chi-Ming Chen ,  Eugene I-Chun Chen ,  Chia-Shiung Tsai

    IPC分类号： H01L21/762

    摘要： A method of forming a semiconductor-on-insulator (SOI) substrate includes: forming a first dielectric layer on a first substrate; forming a buffer layer on a second substrate; forming a semiconductor cap on the buffer layer over the second substrate; forming a cleavage plane in the buffer layer; forming a second dielectric layer on the semiconductor cap after forming the cleavage plane; bonding the second dielectric layer on the second substrate to the first dielectric layer on the first substrate; performing a splitting process along the cleavage plane in the buffer layer; removing a first split buffer layer from the semiconductor cap; and removing a second split buffer layer from the second substrate.

    SOURCE/DRAINS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF
    7.
    发明申请
    SOURCE/DRAINS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF 有权

    公开(公告)号：US20220328640A1

    公开(公告)日：2022-10-13

    申请号：US17854328

    申请日：2022-06-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/788

    摘要： A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.