公开(公告)号：US20190164760A1

公开(公告)日：2019-05-30

申请号：US15824573

申请日：2017-11-28

申请人： Toyota Motor Engineering & Manufacturing North America, Inc.

发明人： Shailesh N. Joshi

IPC分类号： H01L21/20 ,  H01L21/324

CPC分类号： H01L21/2007 ,  H01L21/324 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/1067

摘要： A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.

公开(公告)号：US20170263531A1

公开(公告)日：2017-09-14

申请号：US15175674

申请日：2016-06-07

申请人： Toyota Motor Engineering & Manufacturing North America, Inc.

发明人： Yuji Fukuoka ,  Ercan M. Dede ,  Shailesh N. Joshi ,  Feng Zhou

IPC分类号： H01L23/467 ,  H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/20

CPC分类号： H01L23/467 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/3738 ,  H01L23/473 ,  H01L24/48 ,  H01L24/49 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1426

摘要： A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels.

公开(公告)号：US09627349B2

公开(公告)日：2017-04-18

申请号：US14909157

申请日：2013-09-13

申请人： EV GROUP E. THALLNER GMBH

发明人： Markus Wimplinger

IPC分类号： H01L23/00 ,  B81C3/00

CPC分类号： H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

摘要： A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

公开(公告)号：US09312245B2

公开(公告)日：2016-04-12

申请号：US14496140

申请日：2014-09-25

申请人： International Rectifier Corporation

发明人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC分类号： H01L25/07 ,  H01L27/20 ,  H01L23/495 ,  H01L29/20 ,  H01L29/16 ,  H01L29/772 ,  H01L23/00 ,  H01L29/778

CPC分类号： H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

摘要翻译： 一个示例性的公开的实施例包括三端子堆叠管芯封装，其包括层叠在III族氮化物晶体管的顶部的诸如硅PET的场效应晶体管（PET），使得PET的漏极位于电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

公开(公告)号：US20150348887A1

公开(公告)日：2015-12-03

申请号：US14825382

申请日：2015-08-13

申请人： International Rectifier Corporation

发明人： Eung San Cho ,  Andrew N. Sawle ,  Mark Pavier ,  Daniel Cutler

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L21/84 ,  H01L21/4825 ,  H01L21/4871 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/072 ,  H01L25/117 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24245 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/10325 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10341 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/10355 ,  H01L2924/10356 ,  H01L2924/10357 ,  H01L2924/10358 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

摘要： In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

摘要翻译： 在一个实施方案中，半导体封装包括具有裸片侧的控制导电载体和将半导体封装连接到安装表面的相反的输入/输出（I / O）侧。 半导体封装还包括功率转换器开关级的控制FET，其具有附着到控制导电载体的管芯侧的控制漏极。 控制导电载体被配置为将由控制FET产生的热量吸收到安装表面中。 半导体封装包括具有另一管芯侧的同步导电载体和将半导体封装连接到安装表面的另一相对I / O侧，以及功率转换器开关级的同步FET，其具有连接到同步的管芯侧的同步源 导电载体。

公开(公告)号：US20150287602A1

公开(公告)日：2015-10-08

申请号：US14747150

申请日：2015-06-23

申请人： Sensor Electronic Technology, Inc.

发明人： Remigijus Gaska ,  Xuhong Hu ,  Michael Shur ,  Mikhail Gaevski

IPC分类号： H01L21/283 ,  H01S5/30 ,  H01L33/40 ,  H01S5/042 ,  H01L31/0224 ,  H01L33/00

CPC分类号： H01L21/283 ,  H01L21/28264 ,  H01L21/28575 ,  H01L23/482 ,  H01L24/03 ,  H01L24/05 ,  H01L29/43 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L29/4966 ,  H01L31/022425 ,  H01L33/40 ,  H01L33/405 ,  H01L33/62 ,  H01L2224/03848 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/051 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2933/0016 ,  H01S5/0425 ,  H01S5/3013 ,  H01L2924/00

摘要： A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

摘要翻译： 提供了与包括Cr，Ti和Al的连续层的半导体的接触，其可以导致与基于Ti / Al和Cr / Al的触点相关的一个或多个优点的接触。 例如，触点可以：降低接触电阻; 提供改进的表面形态; 提供更好的接触线性; 和/或要求较低的退火温度，与现有技术的Ti / Al基触点相比。

公开(公告)号：US20150236214A1

公开(公告)日：2015-08-20

申请号：US14704334

申请日：2015-05-05

申请人： Michael A. Tischler ,  Philippe Schick ,  Ian Ashdown ,  Calvin Wade Sheen ,  Paul Jungwirth

发明人： Michael A. Tischler ,  Philippe Schick ,  Ian Ashdown ,  Calvin Wade Sheen ,  Paul Jungwirth

IPC分类号： H01L33/44 ,  H01L33/62 ,  H01L33/48 ,  H01L33/32

CPC分类号： F21K9/66 ,  F21K9/20 ,  F21K9/275 ,  F21K9/278 ,  F21K9/64 ,  F21K9/65 ,  F21V3/02 ,  F21V9/30 ,  F21V23/003 ,  F21V23/02 ,  F21V29/74 ,  F21Y2115/10 ,  G02F1/133603 ,  H01L23/367 ,  H01L23/4985 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0753 ,  H01L27/156 ,  H01L31/0468 ,  H01L33/0025 ,  H01L33/06 ,  H01L33/08 ,  H01L33/28 ,  H01L33/30 ,  H01L33/32 ,  H01L33/36 ,  H01L33/483 ,  H01L33/486 ,  H01L33/502 ,  H01L33/505 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L51/0097 ,  H01L2224/06102 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/10321 ,  H01L2924/10322 ,  H01L2924/10323 ,  H01L2924/10324 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/381 ,  H02S30/00 ,  H05B33/0854 ,  H05B37/0218 ,  H05B37/0227 ,  H05B37/0245 ,  H05K1/189 ,  H05K3/323 ,  H05K2201/09036 ,  H05K2201/10106 ,  H05K2203/302 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01051 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

摘要： In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.

摘要翻译： 根据某些实施例，尽管半导体管芯的表面具有任何非平面性或半导​​体管芯接触件的非共面性，半导体管芯也用压力激活的粘合剂直接粘附到屈服基底上。

公开(公告)号：US08896107B2

公开(公告)日：2014-11-25

申请号：US13095146

申请日：2011-04-27

申请人： Eung San Cho ,  Chuan Cheah

发明人： Eung San Cho ,  Chuan Cheah

IPC分类号： H01L23/495 ,  H01L23/34 ,  H01L23/00

CPC分类号： H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L25/165 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

摘要翻译： 一个示例性的公开的实施例包括被配置为具有控制晶体管，同步晶体管，用于驱动控制和同步晶体管的驱动器集成电路（IC））的降压转换器的高功率半导体封装，以及电连接 同步晶体管耦合到封装的第一引线框焊盘，其中封装的第一引线框焊盘使用引线键电耦合到控制晶体管的控制源。 导电夹子通过直接机械连接和大的表面积传导提供控制源和同步排放之间的有效连接。 同步源电和机械地耦合到提供高电流承载能力的第二引线框架，并且具有高可靠性。 与使用用于晶体管互连的引线的常规封装方法相比，所得封装具有显着降低的电阻，外形尺寸，复杂性和成本。

公开(公告)号：US08847408B2

公开(公告)日：2014-09-30

申请号：US13053556

申请日：2011-03-22

申请人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

发明人： Heny Lin ,  Jason Zhang ,  Alberto Guerra

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L23/00 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L25/074 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/69 ,  H01L24/72 ,  H01L24/73 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/772 ,  H01L29/778 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10334 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

摘要翻译： 一个示例性的公开的实施例包括三端堆叠管芯封装，其包括堆叠在III族氮化物晶体管顶部的场效应晶体管（FET），例如硅FET，使得FET的漏极驻留在电耦合到 III族氮化物晶体管的源极。 封装的第一端子耦合到FET的栅极，封装的第二端子耦合到III族氮化物晶体管的漏极。 封装的第三端子耦合到FET的源极。 以这种方式，诸如级联开关的器件可以以堆叠的管芯形式被封装，从而与常规封装相比，减小了寄生电感和电阻，改善的散热，更小的外形尺寸和更低的制造成本。

公开(公告)号：US20140175664A1

公开(公告)日：2014-06-26

申请号：US13724426

申请日：2012-12-21

申请人： CREE, INC.

发明人： Helmut Hagleitner ,  Fabian Radulescu

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5384 ,  H01L21/28506 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/26145 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/83007 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2924/00014

摘要： The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.

摘要翻译： 本公开涉及一种用于半导体管芯的电介质阻焊层。 在一个实施例中，半导体管芯包括衬底，在衬底的第一表面上的半导体本体，与衬底相对的半导体本体上的一个或多个第一金属化层，从衬底的第二表面延伸穿过衬底的通孔 并且所述半导体本体连接到所述一个或多个第一金属化层，以及在所述衬底的所述第二表面上和所述通孔内的第二金属化层。 通孔内的第二金属化层的一部分提供第二金属化层与一个或多个第一金属化层之间的电连接。 半导体管芯还包括在第二金属化层上的电介质焊料阻挡层。 优选地，电介质焊料阻挡层位于通孔内的第二金属化层部分的表面上。