公开(公告)号：US20240322013A1

公开(公告)日：2024-09-26

申请号：US18188964

申请日：2023-03-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Fu LU ,  Chih-Hao Wang ,  Wang-Chun Huang ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66666 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391

摘要： A method for manufacturing a semiconductor structure includes forming first and second channel layers over a substrate, forming first source/drain features over the first and second channel layers, forming a gate dielectric layer wrapping around the first and second channel layers, forming a first work function layer wrapping around the gate dielectric layer, forming a hard mask layer wrapping around the first work function layer, removing portions of the hard mask layer and the first work function layer, removing the hard mask layer and the first work function layer wrapping around the second channel layer, removing the hard mask layer wrapping around the first channel layer, forming a second work function layer wrapping around the first work function layer and the second channel layer, forming a metal material between the second work function layer, and forming second source/drain features under the first and second channel layers.

公开(公告)号：US12040191B2

公开(公告)日：2024-07-16

申请号：US18069315

申请日：2022-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

摘要： A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

公开(公告)号：US11637195B2

公开(公告)日：2023-04-25

申请号：US17087131

申请日：2020-11-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

摘要： A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.

公开(公告)号：US11626327B2

公开(公告)日：2023-04-11

申请号：US17097578

申请日：2020-11-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kuo-Cheng Chiang ,  Chung-Wei Hsu ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/308 ,  H01L21/033 ,  H01L21/28 ,  H01L29/78

摘要： A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

公开(公告)号：US20220140115A1

公开(公告)日：2022-05-05

申请号：US17087131

申请日：2020-11-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A method of fabricating a device includes providing a fin extending from a substrate, the fin having a plurality of semiconductor layers and a first distance between each adjacent semiconductor layers. The method further includes providing a dielectric fin extending from the substrate where the dielectric fin is adjacent to the plurality of semiconductor layers and there is a second distance between an end of each of the semiconductor layers and a first sidewall of the dielectric fin. The second distance is greater than the first distance. Depositing a dielectric layer over the semiconductor layers and over the first sidewall of the dielectric fin. Forming a first metal layer over the dielectric layer on the semiconductor layers and on the first sidewall of the dielectric fin, wherein portions of the first metal layer disposed on and interposing adjacent semiconductor layers are merged together. Finally removing the first metal layer.

公开(公告)号：US20220140097A1

公开(公告)日：2022-05-05

申请号：US17228922

申请日：2021-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

摘要： A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

公开(公告)号：US20170084717A1

公开(公告)日：2017-03-23

申请号：US15368346

申请日：2016-12-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hsiang Fan ,  Chun-Hsiung Lin ,  Mao-Lin Huang

IPC分类号： H01L29/66 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/306 ,  H01L29/08

CPC分类号： H01L29/66462 ,  H01L21/30617 ,  H01L29/0843 ,  H01L29/0891 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/7784

摘要： An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.

公开(公告)号：US20240355625A1

公开(公告)日：2024-10-24

申请号：US18758948

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/28185 ,  H01L21/02603 ,  H01L21/0332 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78696

摘要： A structure includes first nanostructures vertically spaced one from another over a substrate in a core region of the semiconductor structure, a first interfacial layer wrapping around each of the first nanostructures, a first high-k dielectric layer over the first interfacial layer and wrapping around each of the first nanostructures, second nanostructures vertically spaced one from another over the substrate in an I/O region of the semiconductor structure, a second interfacial layer wrapping around each of the second nanostructures, a second high-k dielectric layer over the second interfacial layer and wrapping around each of the second nanostructures. The first nanostructures have a first vertical pitch, the second nanostructures have a second vertical pitch substantially equal to the first vertical pitch, the first nanostructures have a first vertical spacing, the second nanostructures have a second vertical spacing greater than the first vertical spacing by about 4 Å to about 20 Å.

公开(公告)号：US11996334B2

公开(公告)日：2024-05-28

申请号：US18069052

申请日：2022-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Jia-Ni Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L21/823857 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0669 ,  H01L29/42392

摘要： A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

公开(公告)号：US11901361B2

公开(公告)日：2024-02-13

申请号：US17814842

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/02 ,  H01L27/11 ,  H01L29/786 ,  H10B10/00

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/78696 ,  H10B10/12

摘要： A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.