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    Low leakage capacitor for analog floating-gate integrated circuits
    1.
    发明授权
    Low leakage capacitor for analog floating-gate integrated circuits 有权
    用于模拟浮栅集成电路的低漏电容

    公开(公告)号：US08729616B2

    公开(公告)日：2014-05-20

    申请号：US13718485

    申请日：2012-12-18

    Applicant: Texas Instruments Incorporated

    Inventor： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

    IPC: H01L29/94

    CPC classification number: H01L29/94 ,  G11C27/005 ,  G11C2216/10 ,  H01L27/1156 ,  H01L27/11803 ,  H01L28/40 ,  H01L28/60 ,  H01L29/7883 ,  H01L29/8616

    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

    Electrically erasable programmable non-volatile memory
    2.
    发明授权
    Electrically erasable programmable non-volatile memory 有权
    电可擦除可编程非易失性存储器

    公开(公告)号：US08546222B1

    公开(公告)日：2013-10-01

    申请号：US13899369

    申请日：2013-05-21

    Applicant: Texas Instruments Incorporated

    Inventor： Shanjen Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC: H01L21/336

    CPC classification number: H01L27/0733 ,  H01L21/82 ,  H01L23/525 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

    Abstract translation: 在本发明的实施例中，公开了制造浮栅PMOSFET（p型金属氧化物半导体场效应晶体管）的方法。 硅化物阻挡层（例如氧化物，氮化物）不仅用于阻挡不被硅化的区域，而且还在多晶硅栅极的顶部形成绝缘体。 绝缘体与顶部电极（控制栅极）一起形成在多晶硅栅极顶部的电容器。 多晶硅栅极还用于电容器的底部电极。 然后可以使用电容器将电荷电容耦合到多晶硅栅极。 由于多晶硅栅极被绝缘材料包围，所以耦合到多晶硅栅极的电荷可以在编程操作之后长时间存储。

    Reducing Retention Loss in Analog Floating Gate Memory
    3.
    发明申请
    Reducing Retention Loss in Analog Floating Gate Memory 审中-公开
    减少模拟浮动存储器中的保留损耗

    公开(公告)号：US20150364480A1

    公开(公告)日：2015-12-17

    申请号：US14546009

    申请日：2014-11-18

    Applicant: Texas Instruments Incorporated

    Inventor： Allan T. Mitchell

    IPC: H01L27/115 ,  H01L21/326 ,  H01L21/324

    CPC classification number: H01L21/326 ,  G11C16/0441 ,  G11C29/50004 ,  G11C2029/0403 ,  H01L21/324 ,  H01L22/14 ,  H01L22/20 ,  H01L27/11558

    Abstract: A conditioning process for integrated circuits including floating-gate devices, such as floating-gate capacitors or transistors in analog or other circuits in which the devices are to be programmed to a specific level. Following initial programming of the floating-gate devices to a specific programmed level, the integrated circuits are subjected to a conditioning bake, followed by re-trim back to the initial programmed level. That portion of the charge at the floating-gate device that was weakly held is removed by the conditioning bake, while the re-trim replaces that charge with more strongly held (i.e., higher activation energy) programmed charge.

    Abstract translation: 集成电路的调理过程包括浮动栅极器件，例如模拟或其他电路中的浮栅电容器或晶体管，其中器件将被编程到特定的电平。 在将浮栅器件初始编程到特定编程电平之后，集成电路经受调节烘烤，然后重新修整回初始编程级。 通过调理烘烤将浮动栅极器件中弱电位的电荷部分除去，而重新修整则以较强的保持（即较高的激活能量）编程的电荷取代该电荷。

    LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS
    4.
    发明申请
    LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS 有权
    用于模拟浮动门集成电路的低泄漏电容

    公开(公告)号：US20130130450A1

    公开(公告)日：2013-05-23

    申请号：US13718485

    申请日：2012-12-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

    IPC: H01L29/94

    CPC classification number: H01L29/94 ,  G11C27/005 ,  G11C2216/10 ,  H01L27/1156 ,  H01L27/11803 ,  H01L28/40 ,  H01L28/60 ,  H01L29/7883 ,  H01L29/8616

    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

    Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors
    7.
    发明授权
    Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors 有权
    实现n沟道和p沟道MOS晶体管的模拟浮栅存储器制造工艺

    公开(公告)号：US09064903B2

    公开(公告)日：2015-06-23

    申请号：US14172608

    申请日：2014-02-04

    Applicant: Texas Instruments Incorporated

    Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

    IPC: H01L27/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L23/522 ,  H01L27/115 ,  H01L49/02 ,  H01L29/94

    CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

    NON-VOLATILE ANTI-FUSE WITH CONSISTENT RUPTURE
    8.
    发明申请
    NON-VOLATILE ANTI-FUSE WITH CONSISTENT RUPTURE 审中-公开
    具有一致性破坏的非易失性抗熔丝

    公开(公告)号：US20140239409A1

    公开(公告)日：2014-08-28

    申请号：US14268493

    申请日：2014-05-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

    IPC: H01L27/112

    CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

    Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

    Non-volatile anti-fuse with consistent rupture
    9.
    发明授权
    Non-volatile anti-fuse with consistent rupture 有权
    不挥发性反熔丝具有一致的破裂

    公开(公告)号：US09257440B2

    公开(公告)日：2016-02-09

    申请号：US14268493

    申请日：2014-05-02

    Applicant: Texas Instruments Incorporated

    Inventor： Allan T. Mitchell ,  Mark A. Eskew ,  Keith Jarreau

    IPC: H01L27/112 ,  G11C17/16 ,  H01L29/49 ,  H01L29/861

    CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L27/11226 ,  H01L29/4983 ,  H01L29/861

    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.

    Abstract translation: 在本发明的实施例中，公开了一种非易失性反熔丝存储器单元。 存储单元由可编程的n沟道二极管连接晶体管组成。 晶体管的多晶硅栅极具有两部分。 一部分掺杂比第二部分更高。 晶体管还具有源的两部分，其中源的一部分被掺杂得比第二部分更高。 物理上更接近源极的栅极的部分比多晶硅栅极的其他部分更轻掺杂。 物理上更靠近聚硅氧烷栅极的轻掺杂部分的源的部分相对于源的另一部分被轻掺杂。 当晶体管被编程时，在重掺杂的聚硅氧烷栅极的部分中绝大多数情况下会发生破裂。

    ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY
    10.
    发明申请
    ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY 有权
    电可擦除可编程非易失性存储器

    公开(公告)号：US20130256773A1

    公开(公告)日：2013-10-03

    申请号：US13899369

    申请日：2013-05-21

    Applicant: Texas Instruments Incorporated

    Inventor： Shanjen Pan ,  Allan T. Mitchell ,  Weidong Tian

    IPC: H01L27/07 ,  H01L23/525 ,  H01L21/82

    CPC classification number: H01L27/0733 ,  H01L21/82 ,  H01L23/525 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

    Abstract translation: 在本发明的实施例中，公开了制造浮栅PMOSFET（p型金属氧化物半导体场效应晶体管）的方法。 硅化物阻挡层（例如氧化物，氮化物）不仅用于阻挡不被硅化的区域，而且还在多晶硅栅极的顶部形成绝缘体。 绝缘体与顶部电极（控制栅极）一起形成在多晶硅栅极顶部的电容器。 多晶硅栅极还用于电容器的底部电极。 然后可以使用电容器将电荷电容耦合到多晶硅栅极。 由于多晶硅栅极被绝缘材料包围，所以耦合到多晶硅栅极的电荷可以在编程操作之后长时间存储。

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