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    Plasma treatment for thin film resistors on integrated circuits
    1.
    发明授权
    Plasma treatment for thin film resistors on integrated circuits 有权

    公开(公告)号：US10276648B1

    公开(公告)日：2019-04-30

    申请号：US15855576

    申请日：2017-12-27

    Applicant: Texas Instruments Incorporated

    Inventor： Kaiping Liu ,  Imran Mahmood Khan

    IPC: H01L21/00 ,  H01L49/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/11509 ,  H01L27/11507

    Abstract: A method of fabricating ICs including thin film resistors (TFRs) depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry comprising a plurality of interconnected transistors. A TFR layer comprising chromium (Cr) is deposited on the dielectric liner layer. The TFR layer is plasma treated with atomic nitrogen and atomic hydrogen. A dielectric capping layer is deposited on the TFR layer after the plasma treating. A pattern is formed on the capping layer, and the TFR layer is etched to form at least one resistor that comprises the TFR layer.

    Low leakage capacitor for analog floating-gate integrated circuits
    5.
    发明授权
    Low leakage capacitor for analog floating-gate integrated circuits 有权
    用于模拟浮栅集成电路的低漏电容

    公开(公告)号：US08729616B2

    公开(公告)日：2014-05-20

    申请号：US13718485

    申请日：2012-12-18

    Applicant: Texas Instruments Incorporated

    Inventor： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

    IPC: H01L29/94

    CPC classification number: H01L29/94 ,  G11C27/005 ,  G11C2216/10 ,  H01L27/1156 ,  H01L27/11803 ,  H01L28/40 ,  H01L28/60 ,  H01L29/7883 ,  H01L29/8616

    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

    High precision capacitor dielectric
    6.
    发明授权
    High precision capacitor dielectric 有权
    高精度电容电容

    公开(公告)号：US09496327B2

    公开(公告)日：2016-11-15

    申请号：US15008619

    申请日：2016-01-28

    Applicant: Texas Instruments Incorporated

    Inventor： John Paul Campbell ,  Kaiping Liu

    IPC: H01L21/28 ,  H01L49/02 ,  H01L21/321 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/06 ,  H01L21/02 ,  H01L21/027

    CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/28035 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3211 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/0629

    Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

    Abstract translation: 形成集成电路的工艺形成具有金属表面的高精度电容器底板，并执行金属表面的等离子体处理。 通过在第一层为氮化硅的高精度电容器底板上沉积电容器电介质的第一层而形成高精度电容器电介质，在第一层上沉积第二层电容器电介质，其中第二部分是二氧化硅 并且在第二部分上沉积电容器电介质的第三层，其中第三层是氮化硅。 也可以在电容器电介质预沉积和/或沉积后的层上进行等离子体处理。 在高精度电容器电介质上形成金属高精度电容器顶板。

    LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS
    8.
    发明申请
    LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS 有权
    用于模拟浮动门集成电路的低泄漏电容

    公开(公告)号：US20130130450A1

    公开(公告)日：2013-05-23

    申请号：US13718485

    申请日：2012-12-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Imran Mahmood Khan ,  Allan T. Mitchell ,  Kaiping Liu

    IPC: H01L29/94

    CPC classification number: H01L29/94 ,  G11C27/005 ,  G11C2216/10 ,  H01L27/1156 ,  H01L27/11803 ,  H01L28/40 ,  H01L28/60 ,  H01L29/7883 ,  H01L29/8616

    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

    Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

    THIN FILM RESISTOR INTEGRATION IN COPPER DAMASCENE METALLIZATION
    9.
    发明申请
    THIN FILM RESISTOR INTEGRATION IN COPPER DAMASCENE METALLIZATION 审中-公开
    铜薄膜电容器中的薄膜电容器集成

    公开(公告)号：US20160218062A1

    公开(公告)日：2016-07-28

    申请号：US14604660

    申请日：2015-01-23

    Applicant: Texas Instruments Incorporated

    Inventor： Rajni J. Aggarwal ,  John P. Campbell ,  Kaiping Liu ,  Weidong Tian

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L23/528 ,  H01L23/29

    CPC classification number: H01L23/5228 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit with copper damascene interconnects includes a thin film resistor. Copper damascene metal lines are formed in a first ILD layer. A dielectric layer including an etch stop layer is formed on the first ILD layer and metal lines. Resistor heads of refractory metal are formed in the dielectric layer so that edges of the resistor heads are substantially coplanar with the adjacent dielectric layer. A thin film resistor layer is formed on the dielectric layer, extending onto the resistor heads. A second ILD layer is formed over the dielectric layer and the thin film resistor layer. Copper damascene vias are formed in the second ILD layer, making contact to the metal lines in the first ILD layer. Connections to the resistor heads are provided by the metal lines and/or the vias.

    Abstract translation: 具有铜镶嵌互连的集成电路包括薄膜电阻器。 铜镶嵌金属线形成在第一ILD层中。 在第一ILD层和金属线上形成包括蚀刻停止层的电介质层。 难熔金属的电阻头形成在电介质层中，使得电阻头的边缘与相邻的电介质层基本上共面。 在电介质层上形成薄膜电阻层，延伸到电阻头上。 在电介质层和薄膜电阻层上形成第二ILD层。 在第二ILD层中形成铜大马士革通孔，与第一ILD层中的金属线接触。 与电阻头的连接由金属线和/或通孔提供。

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