公开(公告)号：US10276648B1

公开(公告)日：2019-04-30

申请号：US15855576

申请日：2017-12-27

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Imran Mahmood Khan

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L27/11509 ,  H01L27/11507

Abstract: A method of fabricating ICs including thin film resistors (TFRs) depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry comprising a plurality of interconnected transistors. A TFR layer comprising chromium (Cr) is deposited on the dielectric liner layer. The TFR layer is plasma treated with atomic nitrogen and atomic hydrogen. A dielectric capping layer is deposited on the TFR layer after the plasma treating. A pattern is formed on the capping layer, and the TFR layer is etched to form at least one resistor that comprises the TFR layer.

公开(公告)号：US09064903B2

公开(公告)日：2015-06-23

申请号：US14172608

申请日：2014-02-04

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L23/522 ,  H01L27/115 ,  H01L49/02 ,  H01L29/94

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

公开(公告)号：US08975135B2

公开(公告)日：2015-03-10

申请号：US14301766

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Amitava Chatterjee ,  Imran Mahmood Khan

IPC: H01L21/8242 ,  H01L29/66 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L29/66181 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11558 ,  H01L28/60

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹 在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

公开(公告)号：US20130341759A1

公开(公告)日：2013-12-26

申请号：US13918388

申请日：2013-06-14

Applicant: Texas Instruments Incorporated

Inventor： Imran Mahmood Khan ,  John Paul Campbell ,  Neal Thomas Murphy

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.

Abstract translation: 具有高精度MIM电容器和高精度电阻器的集成电路，通过电阻器底板材料形成的电阻头上具有通孔蚀刻停止焊盘。 使用与用于形成电容器底板的相同的层形成具有高精度MIM电容器和高精度电阻器的集成电路的工艺，其中通过蚀刻停止在电阻头上方的着色焊盘。

公开(公告)号：US09230887B2

公开(公告)日：2016-01-05

申请号：US14614858

申请日：2015-02-05

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Imran Mahmood Khan ,  Richard Allen Faust

IPC: H01L29/00 ,  H01L23/48 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/50 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

公开(公告)号：US20140154850A1

公开(公告)日：2014-06-05

申请号：US14172608

申请日：2014-02-04

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

公开(公告)号：US09577094B2

公开(公告)日：2017-02-21

申请号：US14885637

申请日：2015-10-16

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/06 ,  H01L21/28 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其在DEMOS栅极下具有较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US09455312B2

公开(公告)日：2016-09-27

申请号：US14949274

申请日：2015-11-23

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Imran Mahmood Khan ,  Richard Allen Faust

IPC: H01L21/20 ,  H01L49/02 ,  H01L23/48 ,  H01L21/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/50 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/486 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

公开(公告)号：US09202912B2

公开(公告)日：2015-12-01

申请号：US14576693

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其具有在DEMOS栅极下方的较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US08754501B2

公开(公告)日：2014-06-17

申请号：US13918388

申请日：2013-06-14

Applicant: Texas Instruments Incorporated

Inventor： Imran Mahmood Khan ,  John Paul Campbell ,  Neal Thomas Murphy

IPC: H01L27/06

CPC classification number: H01L28/60 ,  H01L27/016 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.

Abstract translation: 具有高精度MIM电容器和高精度电阻器的集成电路，通过电阻器底板材料形成的电阻头上具有通孔蚀刻停止焊盘。 使用与用于形成电容器底板的相同的层形成具有高精度MIM电容器和高精度电阻器的集成电路的工艺，其中通过蚀刻停止在电阻头上方的着色焊盘。