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    MULTILEVEL PACKAGE SUBSTRATE FOR INTERLEVEL DIELECTRIC CRACK MITIGATION
    1.
    发明申请
    MULTILEVEL PACKAGE SUBSTRATE FOR INTERLEVEL DIELECTRIC CRACK MITIGATION 有权

    公开(公告)号：US20250006661A1

    公开(公告)日：2025-01-02

    申请号：US18344722

    申请日：2023-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Guangxu Li ,  Sylvester Ankamah-Kusi ,  Rajen Murugan

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

    Abstract: An electronic device includes a multilevel package substrate and a semiconductor die, where the multilevel package substrate has first and second levels in respective first and second planes in a stack, the first level including a first conductive feature, and the second level including a second conductive feature, and the semiconductor die has a conductive peripheral terminal, a conductive interior terminal, a peripheral region, and an interior region. The peripheral region laterally surrounds the interior region and extends laterally between the interior region and the lateral sides of the semiconductor die, the conductive peripheral terminal extends from the peripheral region to the first level, the conductive interior terminal extends from the interior region to the first level, the peripheral terminal is coupled to a peripheral contact portion of the first conductive feature, and the second level has no conductive feature under the peripheral contact portion.

    METAL FILLING AND TOP METAL SPACING FOR DIE CRACK MITIGATION
    2.
    发明申请
    METAL FILLING AND TOP METAL SPACING FOR DIE CRACK MITIGATION 有权

    公开(公告)号：US20250006660A1

    公开(公告)日：2025-01-02

    申请号：US18343824

    申请日：2023-06-29

    Applicant: Texas Instruments Incorporated

    Inventor： Yutaka Suzuki ,  Clinton E. Granger, III ,  Jaimal Williamson ,  Rajen Murugan

    IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522

    Abstract: An electronic device includes a semiconductor die having a semiconductor body, a metallization structure over the semiconductor body and a conductive terminal, the metallization structure including a top level having neighboring first and second top metal structures that extend in a plane of orthogonal first and second directions, the first top metal structure is electrically coupled to the conductive terminal, the conductive terminal extends over a portion of the first top metal structure and away from the plane along a third direction orthogonal to the first and second directions, and the first top metal structure is spaced apart from the second top metal structure in the plane by a spacing distance of 60 μm or more.

    MICROELECTRONIC PACKAGE WITH ANTENNA WAVEGUIDE
    3.
    发明公开
    MICROELECTRONIC PACKAGE WITH ANTENNA WAVEGUIDE 审中-公开

    公开(公告)号：US20240258704A1

    公开(公告)日：2024-08-01

    申请号：US18104124

    申请日：2023-01-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Bakshi

    IPC: H01Q13/00 ,  H01Q1/48 ,  H01Q9/04

    CPC classification number: H01Q13/00 ,  H01Q1/48 ,  H01Q9/0407

    Abstract: A microelectronic package includes a waveguide radiation receiver formed in a first conductor layer of a multilayer package substrate, the multilayer package substrate comprising the first conductor layer spaced from a second conductor layer by a dielectric layer. The microelectronic package further includes a tubular waveguide mounted to the multilayer package substrate such that a central aperture of the tubular waveguide is over the waveguide radiation receiver, and a feed line coupling the waveguide radiation receiver to a transmitter-receiver, the feed line including a conductive via traversing the dielectric layer electrically coupling a first portion of the feed line in the first conductor layer to a second portion of the feed line in the second conductor layer, the first portion adjacent the waveguide radiation receiver, and the second portion adjacent the transmitter-receiver.

    Multi-channel gate driver package with grounded shield metal
    4.
    发明授权
    Multi-channel gate driver package with grounded shield metal 有权

    公开(公告)号：US12191259B2

    公开(公告)日：2025-01-07

    申请号：US17569724

    申请日：2022-01-06

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/495 ,  H01L25/00 ,  H01L25/18 ,  H03K17/042

    Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

    MULTI-CHANNEL GATE DRIVER PACKAGE WITH GROUNDED SHIELD METAL
    9.
    发明公开
    MULTI-CHANNEL GATE DRIVER PACKAGE WITH GROUNDED SHIELD METAL 审中-公开

    公开(公告)号：US20230215811A1

    公开(公告)日：2023-07-06

    申请号：US17569724

    申请日：2022-01-06

    Applicant: Texas Instruments Incorporated

    Inventor： Yiqi Tang ,  Rajen Murugan ,  Jie Chen

    IPC: H01L23/552 ,  H03K17/042 ,  H01L23/495 ,  H01L25/00

    CPC classification number: H01L23/552 ,  H03K17/04206 ,  H01L23/49503 ,  H01L25/50 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48

    Abstract: A multi-channel gate driver package includes a leadframe including a first, second, and third die pad. A transmitter die includes first and second transmitter signal bond pads, a first receiver die including a second signal bond pad, and a second receiver die including a third signal bond pad. A bond wire is between the first transmitter signal bond pad and the second signal bond pad, and between the second transmitter signal bond pad and third signal bond pad. A ring shield is around the respective signal bond pads. A downbond is from the second ring shield to the second die pad, and from the third ring shield to the third die pad. A connection connects the first and second transmitter ring shield to at least one ground pin of the package. The second and third die pad each include a direct integral connection to the ground pin.

    Semiconductor package with electromagnetic interference shielding
    10.
    发明授权
    Semiconductor package with electromagnetic interference shielding 有权

    公开(公告)号：US12165989B2

    公开(公告)日：2024-12-10

    申请号：US18295192

    申请日：2023-04-03

    Applicant: Texas Instruments Incorporated

    Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

    IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

    Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

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