公开(公告)号：US09768078B2

公开(公告)日：2017-09-19

申请号：US15148497

申请日：2016-05-06

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US09178037B2

公开(公告)日：2015-11-03

申请号：US14740438

申请日：2015-06-16

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US20150140769A1

公开(公告)日：2015-05-21

申请号：US14609051

申请日：2015-01-29

Applicant: Texas Instruments Incorporated

Inventor： Seung-Chul Song ,  James W. Blatchford ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Abstract translation: 凸起的源极/漏极MOS晶体管形成在利用第一侧壁间隔物的过程中，当注入半导体区域以形成晶体管的重掺杂源极区域和重掺杂漏极区域时，以及第二不同侧壁间隔物，当外延 生长晶体管的升高的源极区域和升高的漏极区域。

公开(公告)号：US20140183663A1

公开(公告)日：2014-07-03

申请号：US13729282

申请日：2012-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Seung-Chul Song ,  James W. Blatchford ,  Kwan-Yong Lim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Abstract translation: 凸起的源极/漏极MOS晶体管形成在利用第一侧壁间隔物的过程中，当注入半导体区域以形成晶体管的重掺杂源极区域和重掺杂漏极区域时，以及第二不同侧壁间隔物，当外延 生长晶体管的升高的源极区域和升高的漏极区域。

公开(公告)号：US20160172443A1

公开(公告)日：2016-06-16

申请号：US14967199

申请日：2015-12-11

Applicant: Texas Instruments Incorporated

Inventor： Younsung Choi ,  Kwan-Yong Lim ,  Seung-Chul Song ,  Song Zhao

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L29/4916 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for tuning a threshold voltage of a semiconductor device includes implanting at least one dopant in a semiconductor substrate at an angle to form a source region and/or a drain region of a transistor. The angle is oblique to a surface of the substrate. Implanting the at least one dopant at the angle alters a flat-band voltage of the transistor and shifts the threshold voltage of the transistor. The at least one dopant or at least one additional dopant can be implanted in a gate electrical contact of the transistor. Implanting the at least one dopant at the oblique angle can change an electrostatic potential of a gate electrical contact of the transistor compared to implanting the at least one dopant at a non-oblique angle, and the change in the electrostatic potential of the gate electrical contact can shift the threshold voltage of the transistor.

Abstract translation: 用于调整半导体器件的阈值电压的方法包括以一定角度在半导体衬底中注入至少一种掺杂剂以形成晶体管的源极区和/或漏极区。 该角度与衬底的表面倾斜。 以角度植入至少一种掺杂剂会改变晶体管的平带电压并使晶体管的阈值电压发生偏移。 可以将至少一种掺杂剂或至少一种附加掺杂剂注入到晶体管的栅极电接触中。 以倾斜角度植入所述至少一种掺杂剂可以改变晶体管的栅极电接触的静电电位，以便以非倾斜角度注入至少一种掺杂剂，并且栅极电接触的静电电位的变化 可以移动晶体管的阈值电压。

公开(公告)号：US09362375B2

公开(公告)日：2016-06-07

申请号：US14740431

申请日：2015-06-16

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

公开(公告)号：US09224656B2

公开(公告)日：2015-12-29

申请号：US13950909

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用烃试剂形成的含碳氮化硅。 硬掩模的第二层是使用氯化硅烷试剂在第一层上形成的含氯氮化硅。 在形成SiGe外延源极/漏极区之后，使用湿法蚀刻去除硬掩模，其以比第一层至少三倍的速率除去第二层。

公开(公告)号：US09178038B2

公开(公告)日：2015-11-03

申请号：US14609051

申请日：2015-01-29

Applicant: Texas Instruments Incorporated

Inventor： Seung-Chul Song ,  James W. Blatchford ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/265 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.

Abstract translation: 凸起的源极/漏极MOS晶体管形成在利用第一侧壁间隔物的过程中，当注入半导体区域以形成晶体管的重掺杂源极区域和重掺杂漏极区域时，以及第二不同侧壁间隔物，当外延 生长晶体管的升高的源极区域和升高的漏极区域。

公开(公告)号：US09093555B2

公开(公告)日：2015-07-28

申请号：US13950842

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用卤化硅烷试剂形成的含卤素的氮化硅。 硬掩模的第二层是使用无卤试剂在第一层上形成的氮化硅。 在PMOS晶体管中蚀刻源极/漏极空腔之后，进行具有氢的预外延烘烤。 在形成SiGe外延源极/漏极区之后，去除硬掩模。

公开(公告)号：US09659825B2

公开(公告)日：2017-05-23

申请号：US14746106

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.