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公开(公告)号：US20210005270A1
公开(公告)日：2021-01-07
申请号：US17026904
申请日：2020-09-21
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US20210217481A1
公开(公告)日：2021-07-15
申请号：US17219003
申请日：2021-03-31
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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Patent Agency Ranking
公开(公告)号：US20180005698A1
公开(公告)日：2018-01-04
申请号：US15639411
申请日：2017-06-30
Applicant: Toshiba Memory Corporation
Inventor： Koki UENO , Yasuhiro SHIINO , Asuka KANEDA
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621
Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.
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公开(公告)号：US20190108885A1
公开(公告)日：2019-04-11
申请号：US16209520
申请日：2018-12-04
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US20190019559A1
公开(公告)日：2019-01-17
申请号：US16134573
申请日：2018-09-18
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Koki UENO , Yasuhiro SHIINO , Asuka KANEDA
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621
Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.
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公开(公告)号：US20180268906A1
公开(公告)日：2018-09-20
申请号：US15699370
申请日：2017-09-08
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIMURA , Tomoki HIGASHI , Sumito OHTSUKI , Junichi KIJIMA , Keisuke YONEHAMA , Shinichi OOSERA , Yuki KANAMORI , Hidehiro SHIGA , Koki UENO
CPC classification number: G11C16/08 , G11C7/20 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C16/32
Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.
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公开(公告)号：US20180197616A1
公开(公告)日：2018-07-12
申请号：US15915129
申请日：2018-03-08
Applicant: Toshiba Memory Corporation
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC classification number: G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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