中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.015 seconds)

    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20180005698A1

    公开(公告)日：2018-01-04

    申请号：US15639411

    申请日：2017-06-30

    Applicant: Toshiba Memory Corporation

    Inventor： Koki UENO ,  Yasuhiro SHIINO ,  Asuka KANEDA

    IPC: G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190108885A1

    公开(公告)日：2019-04-11

    申请号：US16209520

    申请日：2018-12-04

    Applicant: Toshiba Memory Corporation

    Inventor： Yasuhiro SHIINO ,  Eietsu TAKAHASHI ,  Koki UENO

    IPC: G11C16/26 ,  G11C16/14 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20190019559A1

    公开(公告)日：2019-01-17

    申请号：US16134573

    申请日：2018-09-18

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Koki UENO ,  Yasuhiro SHIINO ,  Asuka KANEDA

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200043558A1

    公开(公告)日：2020-02-06

    申请号：US16597242

    申请日：2019-10-09

    Applicant: Toshiba Memory Corporation

    Inventor： Yasuhiro SHIINO ,  Eietsu Takahashi ,  Koki Ueno

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14

    Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200013466A1

    公开(公告)日：2020-01-09

    申请号：US16574637

    申请日：2019-09-18

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yasuhiro SHIINO ,  Eietsu Takahashi

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/28

    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20180068739A1

    公开(公告)日：2018-03-08

    申请号：US15459261

    申请日：2017-03-15

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yasuhiro SHIINO ,  Tomoaki NAKANO ,  Shigefumi IRIEDA ,  Masashi YOSHIDA

    IPC: G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10

    Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210020249A1

    公开(公告)日：2021-01-21

    申请号：US17064053

    申请日：2020-10-06

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yasuhiro SHIINO ,  Eietsu TAKAHASHI

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/28

    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Patent Agency Ranking