摘要:
A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要:
A magnetic memory cell 1 is provided with a magnetic recording layer 10 which is a ferromagnetic layer and a pinned layer 30 connected with the magnetic recording layer 10 through a non-magnetic layer 20. The magnetic recording layer 10 has a magnetization inversion region 13, a first magnetization fixed region 11 and a second magnetization fixed region 12. The magnetization inversion region 13 has a magnetization whose orientation is invertible and overlaps the pinned layer 30. The first magnetization fixed region 11 is connected with a first boundary B1 in the magnetization inversion region 13 and a magnetization orientation is fixed on a first direction. The second magnetization fixed region 12 is connected with a second boundary B2 in magnetization inversion region 13 and a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.
摘要:
A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要:
A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.
摘要:
A semiconductor memory device of the present invention comprises a memory array and a read circuit that reads data of a selected cell. The memory array includes a plurality of memory cells and a reference cell each having a memory element that stores data based on change in resistance value. The read circuit includes: a voltage comparison unit that compares a value corresponding to a sense current from the selected cell with a value corresponding to a reference current from the reference cell; a first switch; and a second switch. Both of the first and second switches are provided at a subsequent stage of a decoder and at a preceding stage of the voltage comparison unit. The second switch circuit controls input of the value corresponding to the sense current to the voltage comparison unit, while the first switch circuit controls input of the value corresponding to the reference current to the voltage comparison unit.
摘要:
A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring.
摘要:
A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要:
A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要:
A semiconductor integrated circuit is provided that can prevent an internal voltage from the voltage generating circuit from varying during a long term. The semiconductor integrated circuit of the present invention includes a voltage generating circuit configured to generate a reference voltage; a function circuit configured to operate by using the reference voltage; a first capacitance connected to a first node between the voltage generating circuit and the function circuit; and a switch provided between the voltage generating circuit and the first node. The switch is in a turned-off state at least for a period during which the function circuit is in an activated state.
摘要:
A magnetic random access memory includes: a first and second wirings, a plurality of third wirings, a plurality of memory cells and a terminating unit. The first and second wirings extend in a Y direction. The plurality of third wirings extends in an X direction. The memory cell is provided correspondingly to an intersection between the first and second wirings and the third wiring. The terminating unit is provided between the plurality of memory cells and connected to the first and second wirings. The memory cell includes transistors and a magnetoresistive element. The transistors are connected in series between the first and second wirings and controlled based on a signal of the third wiring. The magnetoresistive element is connected to a wiring through which the transistors are connected. At a time of a writing operation, when the write current Iw is supplied from one of the first and second wiring to the other through the transistors, the terminating unit grounds the other.