公开(公告)号：US07718527B2

公开(公告)日：2010-05-18

申请号：US12242914

申请日：2008-10-01

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76856 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.

摘要翻译： 提供了一种用于将钴钨帽层集成到半导体器件制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化基底和位于特征底部的第一金属化层，在第一金属化层上形成钴钨帽层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一实施例包括提供具有Cu路径和低k区域的基本上平坦的表面的图案化衬底，以及在Cu路径上形成钴钨帽层。

公开(公告)号：US20100081276A1

公开(公告)日：2010-04-01

申请号：US12242914

申请日：2008-10-01

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/768

CPC分类号： H01L21/76856 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76814 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.

摘要翻译： 提供了一种用于将钴钨帽层集成到半导体器件制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化基底和位于特征底部的第一金属化层，在第一金属化层上形成钴钨帽层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一实施例包括提供具有Cu路径和低k区域的基本上平坦的表面的图案化衬底，以及在Cu路径上形成钴钨帽层。

公开(公告)号：US07846841B2

公开(公告)日：2010-12-07

申请号：US12242900

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

摘要翻译： 提供了一种用于将氮化钴盖层整合到半导体器件的制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化衬底和在特征底部的第一金属化层，在第一金属化层上形成氮化钴覆盖层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一个实施例包括提供具有Cu路径和低k电介质区域的基本平坦表面的图案化衬底，以及相对于低k电介质区域在Cu路径上选择性地形成氮化钴覆盖层。

公开(公告)号：US07799681B2

公开(公告)日：2010-09-21

申请号：US12173814

申请日：2008-07-15

申请人： Kenji Suzuki ,  Frank M. Cerio, Jr. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

发明人： Kenji Suzuki ,  Frank M. Cerio, Jr. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  C23C16/02 ,  C23C16/16 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76868 ,  H01L21/76883

摘要： A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

摘要翻译： 将钌（Ru）金属盖层和改性的Ru金属覆盖层整合到半导体器件的铜（Cu）金属化中以改善块状Cu金属中的电迁移（EM）和应力迁移（SM）的方法。 在一个实施例中，该方法包括提供包含Cu金属表面和电介质层表面的平坦化图案化衬底，在Cu金属表面上沉积第一Ru金属，以及在电介质层表面上沉积额外的Ru金属，其中额外的量 Ru金属少于第一Ru金属的量。 该方法还包括从电介质层表面至少基本上去除额外的Ru金属，以改善在Cu金属表面上的Ru金属覆盖层的选择性形成。 其他实施例还包括将一种或多种类型的改性剂元素结合到电介质层表面，Cu金属表面，Ru金属覆盖层或其组合中。

公开(公告)号：US20100081275A1

公开(公告)日：2010-04-01

申请号：US12242900

申请日：2008-09-30

申请人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

发明人： Tadahiro Ishizaka ,  Shigeru Mizuno ,  Miho Jomen

IPC分类号： H01L21/768

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

摘要翻译： 提供了一种用于将氮化钴盖层整合到半导体器件的制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。 一个实施例包括提供包含形成在低k材料中的凹陷特征的图案化衬底和在特征底部的第一金属化层，在第一金属化层上形成氮化钴覆盖层，在凹陷特征中沉积阻挡层 包括在低k电介质材料和第一钴金属帽层上，并用Cu金属填充凹陷特征。 另一个实施例包括提供具有Cu路径和低k电介质区域的基本平坦表面的图案化衬底，以及相对于低k电介质区域在Cu路径上选择性地形成氮化钴覆盖层。

公开(公告)号：US20100015798A1

公开(公告)日：2010-01-21

申请号：US12173814

申请日：2008-07-15

申请人： Kenji Suzuki ,  Frank M. Cerio, JR. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

发明人： Kenji Suzuki ,  Frank M. Cerio, JR. ,  Miho Jomen ,  Shigeru Mizuno ,  Yasushi Mizusawa ,  Tadahiro Ishizaka

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  C23C16/02 ,  C23C16/16 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76868 ,  H01L21/76883

摘要： A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

摘要翻译： 将钌（Ru）金属盖层和改性的Ru金属覆盖层整合到半导体器件的铜（Cu）金属化中以改善块状Cu金属中的电迁移（EM）和应力迁移（SM）的方法。 在一个实施例中，该方法包括提供包含Cu金属表面和电介质层表面的平坦化图案化衬底，在Cu金属表面上沉积第一Ru金属，以及在电介质层表面上沉积额外的Ru金属，其中额外的量 Ru金属少于第一Ru金属的量。 该方法还包括从电介质层表面至少基本上去除额外的Ru金属，以改善在Cu金属表面上的Ru金属覆盖层的选择性形成。 其他实施例还包括将一种或多种类型的改性剂元素结合到电介质层表面，Cu金属表面，Ru金属覆盖层或其组合中。

公开(公告)号：US07884012B2

公开(公告)日：2011-02-08

申请号：US11864566

申请日：2007-09-28

申请人： Kenji Suzuki ,  Tadahiro Ishizaka ,  Miho Jomen ,  Jonathan Rullan

发明人： Kenji Suzuki ,  Tadahiro Ishizaka ,  Miho Jomen ,  Jonathan Rullan

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76883

摘要： A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal. The exposure to the oxidation source gas can be an air exposure commonly encountered in semiconductor device manufacturing prior to Cu plating.

摘要翻译： 提供了一种用于半导体器件中凹陷特征的无空隙铜（Cu）填充的方法。 该方法包括提供含有凹陷特征的图案化衬底，在图案化衬底上沉积阻挡膜，包括在凹陷特征中，在阻挡膜上沉积Ru金属膜，以及在Ru金属膜上沉积不连续的Cu籽晶层， 其中Cu籽晶层部分地覆盖凹陷特征中的Ru金属膜。 该方法还包括将衬底暴露于氧化Cu籽晶层的氧化源气体和未被Cu籽晶层覆盖的Ru金属膜的部分，在高温下热处理氧化的Cu种子层和氧化的Ru金属膜 真空条件下或在惰性气体存在下活化用于Cu电镀的氧化的Ru金属膜，并用块状Cu金属填充凹陷特征。 暴露于氧化源气体可以是在镀铜之前在半导体器件制造中通常遇到的空气暴露。

公开(公告)号：US20090087981A1

公开(公告)日：2009-04-02

申请号：US11864566

申请日：2007-09-28

申请人： Kenji Suzuki ,  Tadahiro Ishizaka ,  Miho Jomen ,  Jonathan Rullan

发明人： Kenji Suzuki ,  Tadahiro Ishizaka ,  Miho Jomen ,  Jonathan Rullan

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76883

摘要： A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal. The exposure to the oxidation source gas can be an air exposure commonly encountered in semiconductor device manufacturing prior to Cu plating.

摘要翻译： 提供了一种用于半导体器件中凹陷特征的无空隙铜（Cu）填充的方法。 该方法包括提供含有凹陷特征的图案化衬底，在图案化衬底上沉积阻挡膜，包括在凹陷特征中，在阻挡膜上沉积Ru金属膜，以及在Ru金属膜上沉积不连续的Cu籽晶层， 其中Cu籽晶层部分地覆盖凹陷特征中的Ru金属膜。 该方法还包括将衬底暴露于氧化Cu籽晶层的氧化源气体和未被Cu籽晶层覆盖的Ru金属膜的部分，在高温下热处理氧化的Cu种子层和氧化的Ru金属膜 真空条件下或在惰性气体存在下活化用于Cu电镀的氧化的Ru金属膜，并用块状Cu金属填充凹陷特征。 暴露于氧化源气体可以是在镀铜之前在半导体器件制造中通常遇到的空气暴露。

公开(公告)号：US07776740B2

公开(公告)日：2010-08-17

申请号：US12018074

申请日：2008-01-22

申请人： Kenji Suzuki ,  Miho Jomen ,  Jonathan Rullan

发明人： Kenji Suzuki ,  Miho Jomen ,  Jonathan Rullan

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  C23C16/0218 ,  C23C16/16 ,  C23C16/4482 ,  H01L21/28562 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H2, N2, or NH3, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.

摘要翻译： 将低温选择性Ru金属沉积集成到半导体器件制造中的方法，以改善体Cu金属中的电迁移和应力迁移。 该方法包括提供在电介质层中含有凹陷特征的图案化衬底，其中凹陷特征至少基本上被平坦化的本体Cu金属填充，在H 2，N 2存在下热处理本体Cu金属和电介质层， 或NH 3或其组合，并且在热处理的平坦化Cu体上选择性地沉积Ru金属膜。

公开(公告)号：US08247030B2

公开(公告)日：2012-08-21

申请号：US12044191

申请日：2008-03-07

申请人： Kenji Suzuki ,  Atsushi Gomi ,  Miho Jomen

发明人： Kenji Suzuki ,  Atsushi Gomi ,  Miho Jomen

IPC分类号： C23C16/00

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for controlling copper agglomeration on a substrate and for forming void-free bulk copper metal filling of recessed features in integrated circuits. In one embodiment, the method includes providing a substrate having a topography including a top surface and at least one recessed feature comprising at least a sidewall surface and a bottom surface, depositing a barrier film on the substrate topography, and depositing a metal-containing wetting film on the barrier film. The method further includes physical vapor depositing copper metal on the metal-containing wetting film, where the substrate temperature is sufficiently high to form a smooth copper metal seed layer on the metal-containing wetting film. Void-free bulk copper metal may be plated in the at least one recessed feature.

摘要翻译： 提供了一种用于控制基板上的铜附聚并且用于在集成电路中形成凹陷特征的无空隙体铜金属填充物的方法。 在一个实施例中，该方法包括提供具有包括顶表面和至少一个包含至少侧壁表面和底表面的凹陷特征的形貌的基底，在基底形貌上沉积阻挡膜，以及沉积含金属的润湿 电影在屏障胶片上。 该方法还包括在含金属的润湿膜上物理气相沉积铜金属，其中基底温度足够高以在含金属的润湿膜上形成光滑的铜金属种子层。 无孔块体铜金属可以镀在至少一个凹陷特征中。