利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.023 秒)

    METHOD FOR CALCULATING WARPAGE OF BONDED SOI WAFER AND METHOD FOR MANUFACTURING BONDED SOI WAFER
    2.
    发明申请
    METHOD FOR CALCULATING WARPAGE OF BONDED SOI WAFER AND METHOD FOR MANUFACTURING BONDED SOI WAFER 有权
    用于计算粘结SOI波形的波纹的方法和制造粘合SOI波形的方法

    公开(公告)号：US20140186977A1

    公开(公告)日：2014-07-03

    申请号：US14240432

    申请日：2012-08-21

    申请人： Isao Yokokawa ,  Hiroji Aga ,  Yasushi Mizusawa

    发明人： Isao Yokokawa ,  Hiroji Aga ,  Yasushi Mizusawa

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12 ,  G01B11/306 ,  G01B21/20 ,  H01L21/76254 ,  H01L21/76256 ,  H01L22/20

    摘要： A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer.

    摘要翻译： 用于计算接合SOI晶片的翘曲的方法包括：假设外延生长SOI晶片是具有与接合晶片的掺杂剂浓度相同的掺杂剂浓度的硅单晶晶片; 计算在相对于假定的硅单晶晶片进行外延生长时发生的翘曲A; 计算由外延生长SOI晶片的BOX层的厚度引起的翘曲B. 在接合之前确定基底晶片的翘曲的测量值作为翘曲C; 并计算翘曲（A + B + C）的和作为接合的SOI晶片的翘曲。

    Integrated substrate processing in a vacuum processing tool
    6.
    发明授权
    Integrated substrate processing in a vacuum processing tool 有权
    在真空加工工具中集成基板加工

    公开(公告)号：US08034406B2

    公开(公告)日：2011-10-11

    申请号：US11526767

    申请日：2006-09-26

    申请人： Tadahiro Ishizaka ,  Masamichi Hara ,  Yasushi Mizusawa

    发明人： Tadahiro Ishizaka ,  Masamichi Hara ,  Yasushi Mizusawa

    IPC分类号： C23C16/00 ,  C23C14/00

    CPC分类号： C23C16/54 ,  C23C14/566

    摘要： A method and system are provided for integrated substrate processing in Cu metallization. The method includes providing a substrate in a vacuum processing tool containing a plurality of processing systems configured to process the substrate and a substrate transfer system configured to transfer the substrate under vacuum conditions between the plurality of processing systems, and performing an integrated deposition process on the substrate. The plurality of processing systems and the substrate transfer system maintain a base pressure of background gases at 6.8×10−8 Ton or lower, preferably 5×10−8 Torr or lower, during the integrated deposition process. According to one embodiment, the integrated process includes depositing a barrier metal layer on the substrate, and depositing a Cu layer on the barrier metal layer. According to another embodiment, the integrated process further includes depositing a Ru layer on the barrier metal layer, and depositing a Cu layer on the Ru layer.

    摘要翻译： 提供了用于Cu金属化中的集成基板处理的方法和系统。 该方法包括在真空处理工具中提供衬底，该真空处理工具包含配置成处理衬底的多个处理系统和被配置为在多个处理系统之间的真空条件下传送衬底的衬底传送系统，以及对 基质。 在整个沉积过程中，多个处理系统和基板传送系统将背景气体的基础压力保持在6.8×10-8吨或更低，优选5×10-8托或更低。 根据一个实施例，集成工艺包括在衬底上沉积阻挡金属层，以及在阻挡金属层上沉积Cu层。 根据另一实施例，集成工艺还包括在阻挡金属层上沉积Ru层，以及在Ru层上沉积Cu层。

    METHOD FOR FORMING OXIDE FILM ON SILICON WAFER
    7.
    发明申请
    METHOD FOR FORMING OXIDE FILM ON SILICON WAFER 有权
    硅氧烷膜上形成氧化膜的方法

    公开(公告)号：US20110033958A1

    公开(公告)日：2011-02-10

    申请号：US12921492

    申请日：2009-03-24

    申请人： Tsuyoshi Ohtsuki ,  Satoshi Tobe ,  Yasushi Mizusawa

    发明人： Tsuyoshi Ohtsuki ,  Satoshi Tobe ,  Yasushi Mizusawa

    IPC分类号： H01L21/66

    CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.

    摘要翻译： 本发明提供一种在硅晶片上形成氧化膜的方法，包括：预先测量硅晶片的表面层部分中的硅晶片的表面粗糙度和/或结晶度; 基于测量值调整硅晶片的氧化条件; 以及在调整好的氧化条件下在硅晶片上形成氧化膜。 结果，可以提供形成氧化膜的方法，其可以在形成氧化膜之前甚至基于硅晶片的表面和/或表面层的状态以及甚至超薄氧化物来调节氧化条件 因此可以精确地形成膜。

    Plasma sputtering film deposition method and equipment
    8.
    发明授权
    Plasma sputtering film deposition method and equipment 有权
    等离子体溅射膜沉积方法和设备

    公开(公告)号：US07790626B2

    公开(公告)日：2010-09-07

    申请号：US11577505

    申请日：2005-10-18

    申请人： Taro Ikeda ,  Kenji Suzuki ,  Tatsuo Hatano ,  Yasushi Mizusawa

    发明人： Taro Ikeda ,  Kenji Suzuki ,  Tatsuo Hatano ,  Yasushi Mizusawa

    IPC分类号： H01L21/00

    CPC分类号： H01L21/2855 ,  C23C14/046 ,  C23C14/3471 ,  H01J37/34 ,  H01J2237/3327 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

    摘要： The present invention relates to a technology for depositing a thin metal film by using a plasma sputtering technique on a top surface of a target object, e.g., a semiconductor wafer or the like, and on a surface of a recess opened at the top surface. The film deposition method is characterized in that a film deposition process to deposit a metal film on a sidewall of the recess by generating metal ions by way of making a metal target sputter with a plasma generated from a discharge gas in the processing container and by applying to the mounting table a bias power to cause a metal film deposition based on a metal ion attraction and a sputter etching based on the plasma generated from the discharge gas simultaneously on the top surface of the target object.

    摘要翻译： 本发明涉及通过使用等离子体溅射技术在目标物体（例如半导体晶片等）的顶面上以及在顶面开口的凹部的表面上沉积金属薄膜的技术。 膜沉积方法的特征在于，通过使金属靶溅射在处理容器中由放电气体产生的等离子体溅射金属离子，并且通过应用 在安装台上施加基于金属离子吸引的金属膜沉积和基于从放电气体产生的等离子体在目标物体的顶面上产生的溅射蚀刻的偏置功率。