Linear image sensor with varied electric charge storage time
    1.
    发明授权
    Linear image sensor with varied electric charge storage time 失效
    具有不同电荷存储时间的线性图像传感器

    公开(公告)号:US5337163A

    公开(公告)日:1994-08-09

    申请号:US787948

    申请日:1991-11-05

    CPC分类号: H04N5/3692 H04N1/40056

    摘要: The present invention is directed to a linear image sensor, the electric charge storage time of which can be varied. According to an embodiment of the present invention, there is provided a linear image sensor in which a read-out gate and a charge-transfer gate are disposed on one side of an image sensor array, and a drain gate and a drain region are disposed on the other side of the image sensor array, whereby the electric charge storage time in which a signal charge is transferred by the charge-transfer register after the signal charge is read out by the application of a read-out signal to the read-out gate and the next read-out signal is applied to the read-out gate can be varied by varying the application timing of the drain gate signal. When the linear image sensor is applied to a facsimile, the output level can be adjusted and the light and shade can be controlled by varying the electric charge accumulation time in response to the change of light intensity of a light source or by the change of scan speed of the linear image sensor.

    摘要翻译: 本发明涉及可以改变其电荷储存时间的线性图像传感器。 根据本发明的一个实施例,提供了一种线性图像传感器,其中读出栅极和电荷转移栅极设置在图像传感器阵列的一侧,并且排列栅极和漏极区域被布置 在图像传感器阵列的另一侧上,由此通过向读出的读出信号应用信号电荷后,由电荷转移寄存器传送信号电荷的电荷存储时间 栅极和下一个读出信号被施加到读出门可以通过改变漏极栅极信号的施加定时来改变。 当将线性图像传感器应用于传真机时,可以调节输出电平,并且可以通过响应于光源的光强度的改变或通过扫描的改变来改变电荷累积时间来控制光和阴影 线速图像传感器。

    CCD solid-state pickup device with controlled shutter pulse generation
    2.
    发明授权
    CCD solid-state pickup device with controlled shutter pulse generation 失效
    CCD固态拾取装置,具有受控的快门脉冲产生

    公开(公告)号:US5303052A

    公开(公告)日:1994-04-12

    申请号:US98755

    申请日:1993-07-29

    摘要: A CCD solid-state image pickup device includes a CCD solid-state image pickup element which includes a sensor array comprising a number of one-dimensionally arranged photosensitive units, a read-out gate, a transfer register and electronic shutter means comprising a drain gate and a drain region, the read-out gate and the transfer register being disposed at one side of the sensor array and the electronic shutter means being disposed at the other side of the sensor array, an output level comparator for comparing the output level of each image pickup signal from the CCD solid-state image pickup element with the output level of a predetermined reference signal to output a comparison signal, and a shutter-timing generating unit for generating an output timing of a shutter pulse for a predetermined period on the basis of the comparison signal from the output level comparator, and supplying the shutter pulse to the electronic shutter means of the CCD solid-state image pickup element at the generated output timing.

    摘要翻译: CCD固态摄像装置包括:CCD固体摄像元件,其包括具有多个一维排列的感光单元的传感器阵列,读出门,传送寄存器和电子快门装置,其包括排水门 和漏极区域,读出栅极和传输寄存器设置在传感器阵列的一侧,电子快门装置设置在传感器阵列的另一侧;输出电平比较器,用于将每个 具有预定参考信号的输出电平的来自CCD固态图像拾取元件的图像拾取信号,以输出比较信号;以及快门时序生成单元,用于基于该阈值产生预定时段的快门脉冲的输出定时 来自输出电平比较器的比较信号,并将快门脉冲提供给CCD固态摄像元件的电子快门装置, 激发输出时序。

    Input circuit for CCD delay line
    4.
    发明授权
    Input circuit for CCD delay line 失效
    CCD延时线输入电路

    公开(公告)号:US5087843A

    公开(公告)日:1992-02-11

    申请号:US575381

    申请日:1990-08-30

    CPC分类号: G11C19/285 G11C27/04

    摘要: An input circuit for a charge-coupled device (CCD) delay line is comprised of a semiconductor substrate, a CCD delay line formed on the semiconductor substrate, first and second registers each having substantially the same maximum treating charge amount as that of the CCD delay line and formed on the semiconductor substrate, an input portion of the first register having substantially the same structure as that of the CCD delay line, output portions of the first and second registers having substantially the same structure each other, a control circuit for controlling the second register so that an output signal from the second register becomes a signal corresponding to the maximum treating charge amount, a comparing circuit for comparing output signals of the first and second registers, wherein an output signal of the comparing circuit is fed back to an input source of the input portion of the first register so that the output signal from the first register becomes equal to the output signal from the second register, a voltage of high level of a clock signal is supplied to an input gate of the first register and a voltage of the input source of the first register is supplied to an input source of an input portion of the CCD delay line. Thus, an overflow of charge can be avoided satisfactorily.

    Light source switching type color image scanner
    5.
    发明授权
    Light source switching type color image scanner 失效
    光源切换式彩色图像扫描仪

    公开(公告)号:US5398061A

    公开(公告)日:1995-03-14

    申请号:US960877

    申请日:1992-10-14

    CPC分类号: H04N3/1581 H04N9/045

    摘要: The present invention is directed to a light source switching type color image scanner in which a color signal can be read out at high speed by reducing a read-out time. A red light source (3), a green light source (4) and a blue light source (5) which can be selectively switched are disposed under an original document holder (1) on which an original document (2) is held. Further, there are disposed a mirror (7) and a lens (8) which are used to focus a reflected image of the original document (2) onto a CCD linear image sensor (6). The CCD linear image sensor (6) includes a shutter gate (12) and a shutter drain (13) which are used to reset signal charges of remaining lights from the respective light sources (3), (4) and (5). The reset of a signal charge begins before a next color light source is energized.

    摘要翻译: 本发明涉及一种光源切换式彩色图像扫描仪,其中通过减少读出时间可以高速读出彩色信号。 可以选择性地切换的红色光源(3),绿色光源(4)和蓝色光源(5)被放置在其上保持有原稿(2)的原稿保持器(1)的下方。 此外,设置有用于将原稿(2)的反射图像聚焦到CCD线性图像传感器(6)上的反射镜(7)和透镜(8)。 CCD线性图像传感器(6)包括用于复位来自各个光源(3),(4)和(5)的剩余光的信号电荷的快门门(12)和快门排出(13)。 在下一个彩色光源通电之前,信号电荷的复位开始。

    Charge transfer device having a signal processing circuit for correcting
output voltage
    6.
    发明授权
    Charge transfer device having a signal processing circuit for correcting output voltage 失效
    电荷转移装置具有用于校正输出电压的信号处理电路

    公开(公告)号:US5642162A

    公开(公告)日:1997-06-24

    申请号:US631928

    申请日:1996-04-15

    CPC分类号: H04N5/361 H04N5/3728

    摘要: A charge transfer device includes a circuit which can correct a fluctuated amount of light (charge amount)--output voltage characteristic with accuracy even when fluctuated by the change of temperature and the fluctuation of a power supply voltage. An output voltage characteristic in the standard state corresponding to a reference charge is stored and held in a ROM in advance. An ALU (arithmetic logical unit) corrects the light (charge amount)--output voltage characteristic by using the output voltage characteristic in the standard state corresponding to the reference charge stored in the ROM and the output voltages corresponding to the reference charge inputs from reference charge input portions in an imaging state, and corrects an output voltage (Va) corresponding to a signal charge in a practical imaging state.

    摘要翻译: 电荷转移装置包括可以通过温度变化和电源电压的波动波动而能够精确地校正波动量(充电量) - 输出电压特性的电路。 对应于参考电荷的标准状态的输出电压特性预先存储并保存在ROM中。 ALU(算术逻辑单元)通过使用与存储在ROM中的参考电荷相对应的标准状态下的输出电压特性和对应于参考电荷的参考电荷输入的输出电压来校正光(充电量) - 输出电压特性 输入部分,并且在实际成像状态下校正与信号电荷相对应的输出电压(Va)。

    Charge-to-voltage converter with adjustable conversion factor
    7.
    发明授权
    Charge-to-voltage converter with adjustable conversion factor 失效
    具有可调整转换系数的充电电压转换器

    公开(公告)号:US06310369B1

    公开(公告)日:2001-10-30

    申请号:US08789519

    申请日:1997-01-27

    IPC分类号: H01L24148

    CPC分类号: H01L29/76816 G11C19/285

    摘要: In a floating diffusion output type or a floating gate output type charge-to-voltage converter, the floating diffusion or the floating gate is coupled to one or more diffusion regions by means of one or more switch elements, and such elements are selectively turned on or off in such a manner that the the charge-to-voltage conversion factor is raised to obtain a great voltage amplitude when a small quantity of signal charge is input, or the conversion factor is lowered to obtain a small voltage amplitude when a large quantity of signal charge is input.

    摘要翻译: 在浮动扩散输出型或浮置栅极输出型电荷 - 电压转换器中,浮动扩散或浮动栅极通过一个或多个开关元件耦合到一个或多个扩散区域,并且这些元件选择性地导通 或者使得当输入少量的信号电荷时提高电荷电压转换因子以获得大的电压幅度,或者当大量的转换因子降低以获得小的电压幅度时, 的信号电荷被输入。

    Digital memory means with an accurate reference signal
    8.
    发明授权
    Digital memory means with an accurate reference signal 失效
    数字存储器具有精确的参考信号

    公开(公告)号:US4660176A

    公开(公告)日:1987-04-21

    申请号:US482765

    申请日:1983-04-07

    IPC分类号: G11C19/28 G11C27/04 G11C11/34

    CPC分类号: G11C19/285 G11C27/04

    摘要: A digital memory comprises a charge coupled device (CCD) that includes a reference signal storage section. The digital input to the CCD includes an input reference signal and an information signal having a plurality of data levels, for example, a digital "0" and "1". The input reference signal includes a reference bit at the higher data level. The reference signal storage section divides the level of the reference bit to provide a reference level signal halfway between the two data levels. Thus, any shift in the data levels due, for example, to temperature changes in the CCD, affects the reference level signal to the same degree and the reference level can be kept exactly halfway between the data levels.

    摘要翻译: 数字存储器包括电荷耦合器件(CCD),其包括参考信号存储部分。 到CCD的数字输入包括输入参考信号和具有多个数据电平的信息信号,例如数字“0”和“1”。 输入参考信号包括较高数据电平的参考位。 参考信号存储部分分配参考位的电平以在两个数据电平之间提供参考电平信号。 因此,例如由于CCD中的温度变化导致的数据电平的任何偏移都以相同的程度影响参考电平信号,并且参考电平可以准确地保持在数据电平之间的正中。

    Charge coupled device delay line employing a floating gate or floating
diffusion gate at its intermediate output portion
    9.
    发明授权
    Charge coupled device delay line employing a floating gate or floating diffusion gate at its intermediate output portion 失效
    充电耦合设备延迟线在中间输出部分使用浮动门或浮动扩散门

    公开(公告)号:US5227650A

    公开(公告)日:1993-07-13

    申请号:US824355

    申请日:1992-01-23

    CPC分类号: H01L29/76833 H01L29/76816

    摘要: The present invention is to provide a CCD delay line in which a deterioration of a charge transfer efficiency can be reduced by maintaining a charge amount treated in a charge transfer section provided at the rear stage of an intermediate output section. According to an aspect of the present invention, in a charge transfer device having charge transfer sections of a plurality of stages consisting of electrode pairs of a transfer gate electrode and a storage gate electrode and at least one intermediate output section provided at the rear stage of a charge transfer section of a predetermined stage from the signal input side, a cross-sectional area of at least one of the transfer gate electrode and the storage gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be larger than that in the charge transfer section provided at the front stage of the intermediate output section. Further, the impurity concentration in the region of a semiconductor substrate corresponding to the transfer gate electrode in the charge transfer section provided at the rear stage of the intermediate output section is selected to be lower than that in the charge transfer section provided at the front stage of the intermediate output section, thereby the potential barrier being increased.

    Input structure for charge coupled devices with controllable input bias
    10.
    发明授权
    Input structure for charge coupled devices with controllable input bias 失效
    具有可控输入偏置的电荷耦合器件的输入结构

    公开(公告)号:US5029189A

    公开(公告)日:1991-07-02

    申请号:US102432

    申请日:1987-09-29

    摘要: A charge coupled device employs peak hold circuits for detecting electric charges transferred through reference registers for facilitating automatic iput bias control. The peak hold circuits are respectively connected to a pair of reference registers which are so designed that one of the reference registers has a given maximum rating and the other reference register is adapted to transfer electric charge having a given fraction of the maximum charge rating of the aforementioned one of registers. The peak hold circuits provide peak values of the outputs of the reference registers to a comparator which feedback controls the input bias of the one of the register. This controlled bias is also applied to an input bias for a signal register which is designed for transferring input electric charge.

    摘要翻译: 电荷耦合器件采用峰值保持电路来检测通过参考寄存器传输的电荷,以便于自动iput偏置控制。 峰值保持电路分别连接到一对参考寄存器,其被设计为使得一个参考寄存器具有给定的最大额定值,而另一个参考寄存器适于转移具有给定最大额定电压的给定分数的电荷 上述一个寄存器。 峰值保持电路将参考寄存器的输出的峰值提供给比较器,反馈控制寄存器之一的输入偏置。 该受控偏置也适用于设计用于传输输入电荷的信号寄存器的输入偏置。