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13 条记录 (耗时 0.025 秒)

    Phase locked loop circuit
    1.
    发明授权
    Phase locked loop circuit 失效
    锁相环电路

    公开(公告)号：US5117204A

    公开(公告)日：1992-05-26

    申请号：US708758

    申请日：1991-05-31

    申请人： Tadashi Endo ,  Yasuhiko Sakamoto ,  Haruo Yoshida

    发明人： Tadashi Endo ,  Yasuhiko Sakamoto ,  Haruo Yoshida

    IPC分类号： H03B9/12 ,  H03F3/45 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

    CPC分类号： H03L7/085 ,  H03L7/18

    摘要： By using an EIP source lock counter, a frequency of a Gunn oscillator is stabilized. This increases the frequency stability of a circuit. An oscillation output of the Gunn Oscillator is supplied to the EIP source lock counter, and a phase lock signal indicative of a phase shift of the oscillation frequency from the EIP source lock counter relative to a preset reference frequency is supplied to a driver circuit. The driver circuit includes level shift circuit which level-shifts the phase lock signal thereof. A phase compensation circuit in the driver circuit boosts a gain as well as advances a phase at a high frequency region. The current amplifier circuit amplifies a current amplitude of the output of the level shift circuit, and the amplified output therefrom controls an oscillation frequency of the Gunn oscillator using negative feedback.

    摘要翻译： 通过使用EIP源锁定计数器，Gunn振荡器的频率稳定。 这增加了电路的频率稳定性。 将GUN振荡器的振荡输出提供给EIP源锁定计数器，并且将指示来自EIP源锁定计数器的振荡频率相对于预设参考频率的相位锁定信号提供给驱动器电路。 驱动器电路包括对其锁相信号进行电平移位的电平移位电路。 驱动电路中的相位补偿电路增益增益以及在高频区域前进相位。 电流放大器电路放大电平移位电路的输出的电流幅度，并且其放大的输出使用负反馈来控制耿氏振荡器的振荡频率。

    One-time PROM microcomputer
    2.
    发明授权
    One-time PROM microcomputer 失效
    一次性PROM微电脑

    公开(公告)号：US5398208A

    公开(公告)日：1995-03-14

    申请号：US246713

    申请日：1994-05-20

    申请人： Yasuhiko Sakamoto

    发明人： Yasuhiko Sakamoto

    IPC分类号： G06F15/78 ,  G11C5/14 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18 ,  G11C13/00

    CPC分类号： G11C17/18 ,  G11C5/143

    摘要： An OTP microcomputer of the present invention includes: a PROM 14 having a terminal for receiving signals from a voltage supply Vpp that allows a program to be written therein; a MOS transistor to be used as a resistance or a resistance cable containing a pull-up resistance R4, and an input terminal 11 connected to both the terminal of the PROM and a logic circuit of the microcomputer and connected with the drain of the MOS transistor or one end of the resistance R4. In this arrangement, when a microcomputer mode in which the OTP microcomputer is operated as a normal microcomputer is selected, a voltage Vcc (.vertline.Vpp.vertline.>.vertline.Vcc.vertline.) of a device power supply provided inside the circuit of the microcomputer is supplied to the source of the MOS transistor or the other end of the resistance R4. On the other hand, when an OTP mode in which the PROM is written in with a program is selected, the voltage Vpp of the power supply for allowing a program to be written in is supplied to the source of the MOS transistor or the other end of the resistance R4.

    摘要翻译： 本发明的OTP微计算机包括：具有端子的PROM14，用于从电压源Vpp接收信号，该电压允许在其中写入程序; 用作电阻的MOS晶体管或包含上拉电阻R4的电阻电缆，以及连接到PROM的端子和微型计算机的逻辑电路并与MOS晶体管的漏极连接的输入端子11 或电阻R4的一端。 在这种布置中，当选择OTP微型计算机作为普通微型计算机操作的微型计算机模式时，设置在微计算机的电路内部的装置电源的电压Vcc（| Vpp |> | Vcc |）被提供给 MOS晶体管的源极或电阻R4的另一端。 另一方面，当选择使用程序写入PROM的OTP模式时，将用于允许写入程序的电源的电压Vpp提供给MOS晶体管的源极或另一端 的电阻R4。

    PLL clock signal generation circuit
    3.
    发明申请
    PLL clock signal generation circuit 有权
    PLL时钟信号发生电路

    公开(公告)号：US20050099235A1

    公开(公告)日：2005-05-12

    申请号：US10983649

    申请日：2004-11-09

    申请人： Yasuhiko Sakamoto ,  Yoshihiro Nakao

    发明人： Yasuhiko Sakamoto ,  Yoshihiro Nakao

    IPC分类号： H03L7/089 ,  H03L7/095 ,  H03L7/10 ,  H03L7/197 ,  H03L7/00

    CPC分类号： H03L7/10 ,  H03L7/0891 ,  H03L7/197 ,  Y10S331/02

    摘要： A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (output from a filter circuit) and controls a change of a multiple rate of a divider according to a state of the detected reference voltage. The multiple rate control circuit further outputs control signal LPFOUT for changing a multiple rate so that the PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting the state of reference voltage.

    摘要翻译： 一种PLL时钟信号发生电路，包括相位比较器，电荷泵电路，滤波电路，压控振荡器和分频器，其中还包括多速率控制电路，其检测参考电压的状态（从滤波器输出 电路），并且根据检测到的参考电压的状态来控制分频器的多速率的变化。 多速率控制电路还输出用于改变多重速率的控制信号LPFOUT，使得当通过检测参考电压的状态检测到与能够锁定的区域的偏差时，PLL时钟信号发生电路不会偏离可以锁定的区域 。

    Nonvolatile memory and writing circuit for same
    4.
    发明授权
    Nonvolatile memory and writing circuit for same 失效
    非易失性存储器和写入电路相同

    公开(公告)号：US6137717A

    公开(公告)日：2000-10-24

    申请号：US203304

    申请日：1998-12-01

    申请人： Yasuhiko Sakamoto

    发明人： Yasuhiko Sakamoto

    IPC分类号： G11C16/02 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454

    摘要： A writing circuit for a nonvolatile memory has eight circuit units for bit parallel processing. Each circuit unit has 16 first D flip-flops for address 0 to address F, and one second D flip-flop. The eight circuit units hold in their own 16 first D flip-flops write data of 8 bits fed in bit parallel fashion with respect to each of the 16 addresses. The totally eight second D flip-flops simultaneously hold 8 bits of verify data read from memory cells in bit parallel fashion. In verify operation, in each of the eight circuit units, the write data held in the first D flip-flops are given 16 address attributes, respectively, and compared with the verify data held by the second D flip-flop in an address sequence of the 16 address attributes to make sure of coincidence between the data.

    摘要翻译： 用于非易失性存储器的写入电路具有用于位并行处理的八个电路单元。 每个电路单元具有16个用于地址0到地址F的第一D触发器和一个第二D触发器。 八个电路单元保存在它们自己的16个第一D触发器中，相对于16个地址中的每一个，以比特并行方式馈送8位的写入数据。 总共8个第二个D触发器同时容纳从位存储单元以位并行方式读取的8位验证数据。 在验证操作中，在八个电路单元中的每一个中，保持在第一D触发器中的写入数据分别被赋予16个地址属性，并且与第二D触发器保持的验证数据以地址序列 16个地址属性，以确保数据之间的一致性。

    PLL clock signal generation circuit
    6.
    发明授权
    PLL clock signal generation circuit 有权
    PLL时钟信号发生电路

    公开(公告)号：US07109764B2

    公开(公告)日：2006-09-19

    申请号：US10983649

    申请日：2004-11-09

    申请人： Yasuhiko Sakamoto ,  Yoshihiro Nakao

    发明人： Yasuhiko Sakamoto ,  Yoshihiro Nakao

    IPC分类号： H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/0891 ,  H03L7/197 ,  Y10S331/02

    摘要： A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (output from a filter circuit) and controls a change of a multiple rate of a divider according to a state of the detected reference voltage. The multiple rate control circuit further outputs control signal LPFOUT for changing a multiple rate so that the PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting the state of reference voltage.

    摘要翻译： 一种PLL时钟信号发生电路，包括相位比较器，电荷泵电路，滤波电路，压控振荡器和分频器，其中还包括多速率控制电路，其检测参考电压的状态（从滤波器输出 电路），并且根据检测到的参考电压的状态来控制分频器的多速率的变化。 多速率控制电路还输出用于改变多重速率的控制信号LPFOUT，使得当通过检测参考电压的状态检测到与能够锁定的区域的偏差时，PLL时钟信号发生电路不会偏离可以锁定的区域 。

    Production of imidazole derivatives and novel intermediates of the derivatives
    7.
    发明申请
    Production of imidazole derivatives and novel intermediates of the derivatives 失效
    咪唑衍生物的生产和衍生物的新型中间体

    公开(公告)号：US20050043277A1

    公开(公告)日：2005-02-24

    申请号：US10501801

    申请日：2003-02-18

    申请人： Yasuhiko Sakamoto ,  Takushi Kurihara ,  Shinya Harusawa

    发明人： Yasuhiko Sakamoto ,  Takushi Kurihara ,  Shinya Harusawa

    IPC分类号： C07D401/06 ,  C07F9/6506 ,  A61K31/675

    CPC分类号： C07D401/06 ,  C07F9/6506 ,  Y02P20/55

    摘要： An improvement in the production of imidazole derivatives including histamine H3 agonist immepip and histamine H3 antagonist VUF4929. Desired imidazole derivatives can be easily obtained in high yield by using novel intermediates represented by the general formula (I): (I) wherein R1 is an amino-protecting group; R2 and R3 are each independently hydrogen, lower alkyl, or hydroxylated lower alkyl; R4 is lower alkyl, halogenated lower alkyl, or substituted or unsubstituted phenyl; and A is C1-3 alkylene.

    摘要翻译： 咪唑衍生物的生产改进，包括组胺H3激动剂immepip和组胺H3拮抗剂VUF4929。 通过使用由通式（I）表示的新型中间体，可以容易地获得所需的咪唑衍生物：（I）其中R 1是氨基保护基; R 2和R 3各自独立地为氢，低级烷基或羟基化的低级烷基; R 4是低级烷基，卤代低级烷基或取代或未取代的苯基; A是C 1-3亚烷基。

    Acquisition system for the SDMA/TDMA satellite communication system
    8.
    发明授权
    Acquisition system for the SDMA/TDMA satellite communication system 失效
    SDMA / TDMA卫星通信系统采集系统

    公开(公告)号：US3958083A

    公开(公告)日：1976-05-18

    申请号：US551675

    申请日：1975-02-21

    申请人： Takao Hara ,  Yoshikazu Tsuji ,  Yasuhiko Sakamoto

    发明人： Takao Hara ,  Yoshikazu Tsuji ,  Yasuhiko Sakamoto

    IPC分类号： H04B7/204 ,  H04J3/06 ,  H04B7/20

    CPC分类号： H04B7/2048

    摘要： An acquisition system for the SDMA/TDMA satellite communication system is disclosed in which a synchronization signal receiving time slot and a plurality of data signal receiving time slots, for communication between predetermined groups of earth stations and between the earth stations of each group, are sequentially provided at the satellite based on timing signal in the satellite. An acquisition signal having a plurality of signal burst portions is transmitted from the earth station, with its transmit time slot being shifted in a first sweep mode until one part of the acquisition signal is received by said transmitting earth station. At that time the transmit time slot is shifted in a second sweep mode, whereby a control is made to obtain synchronization of the earth station with the satellite so that the plurality of burst portions in the acquisition signal may be properly communicated to the predetermined groups.Further, an acquisition control is shown to be effectively achieved in the case where the SN ratio of the received acquisition signal is extremely deteriorated or where it is necessary to prevent disturbing another earth station of the same group of earth stations which has already accessed the satellite.

    摘要翻译： 公开了一种用于SDMA / TDMA卫星通信系统的采集系统，其中同步信号接收时隙和多个数据信号接收时隙用于在预定的地球站组之间和每个组的地球站之间进行通信， 基于卫星中的定时信号在卫星上提供。 具有多个信号突发部分的获取信号从地球站发射，其发射时隙以第一扫描模式移位，直到所述发射地球站接收到采集信号的一部分。 此时，发送时隙在第二扫描模式中移位，由此进行控制以获得地球站与卫星的同步，使得采集信号中的多个突发部分可以适当地传送到预定的组。

    Production of imidazole derivatives and novel intermediates of the derivatives
    9.
    发明授权
    Production of imidazole derivatives and novel intermediates of the derivatives 失效
    咪唑衍生物的生产和衍生物的新型中间体

    公开(公告)号：US06951944B2

    公开(公告)日：2005-10-04

    申请号：US10501801

    申请日：2003-02-18

    申请人： Yasuhiko Sakamoto ,  Takushi Kurihara ,  Shinya Harusawa

    发明人： Yasuhiko Sakamoto ,  Takushi Kurihara ,  Shinya Harusawa

    IPC分类号： C07D401/06 ,  C07F9/6506

    CPC分类号： C07D401/06 ,  C07F9/6506 ,  Y02P20/55

    摘要： An improvement in the production of imidazole derivatives including histamine H3 agonist immepip and histamine H3 antagonist VUF4929. Desired imidazole derivatives can be easily obtained in high yield by using novel intermediates represented by the general formula (I): (I) wherein R1 is an amino-protecting group; R2 and R3 are each independently hydrogen, lower alkyl, or hydroxylated lower alkyl; R4 is lower alkyl, halogenated lower alkyl, or substituted or unsubstituted phenyl; and A is C1-3 alkylene

    摘要翻译： 包括组胺H 3激动剂immepip和组胺H 3 N拮抗剂VUF4929的咪唑衍生物的生产的改进。 通过使用由通式（I）表示的新型中间体，可以容易地获得所需的咪唑衍生物：（I）其中R 1是氨基保护基; R 2和R 3各自独立地为氢，低级烷基或羟基化的低级烷基; R 4是低级烷基，卤代低级烷基或取代或未取代的苯基; 且A为C 1-3亚烷基

    Process for producing piperazinesulfonamide derivatives and salts thereof
    10.
    发明授权
    Process for producing piperazinesulfonamide derivatives and salts thereof 失效
    哌嗪磺酰胺衍生物及其盐的制备方法

    公开(公告)号：US06172228B2

    公开(公告)日：2001-01-09

    申请号：US09453223

    申请日：1999-12-03

    申请人： Kenichi Kashima ,  Yasuhiko Sakamoto ,  Yoichiro Ohta ,  Kenji Kawanishi ,  Shigetaka Takemura ,  Yasuko Takemura

    发明人： Kenichi Kashima ,  Yasuhiko Sakamoto ,  Yoichiro Ohta ,  Kenji Kawanishi ,  Shigetaka Takemura ,  Yasuko Takemura

    IPC分类号： C07D40106

    CPC分类号： C07D295/088 ,  C07D213/38

    摘要： A process for advantageously preparing a piperazinesulfonamide derivative represented by the general formula (III): wherein R1 is hydrogen atom, a straight or branched chain alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 4 carbon atoms, a halogen atom, hydroxyl group, trifluoromethyl group, nitro group or amino group; R2 is a phenyl group which may have as substituents on its phenyl ring 1 to 3 groups selected from the group consisting of an alkyl group having 1 to 4 carbon atoms, an alkoxy group having 1 to 4 carbon atoms, a halogen atom, hydroxyl group, trifluoromethyl group, nitro group and amino group, 2-pyridyl group, 3-pyridyl group or 4-pyridyl group; each of R3 and R4 is independently hydrogen atom, a straight or branched chain alkyl group having 1 to 6 carbon atoms, a hydroxyalkyl group having 1 to 4 carbon atoms, a cycloalkyl group having 3 to 8 carbon atoms, or a phenyl group which may be substituted; and Y is an alkylene group having 1 to 12 carbon atoms, and a salt thereof.

    摘要翻译： 一种有利地制备由通式（III）表示的哌嗪磺酰胺衍生物的方法：其中R1是氢原子，具有1至6个碳原子的直链或支链烷基，具有1至4个碳原子的烷氧基，卤素原子 ，羟基，三氟甲基，硝基或氨基; R2是可以在其苯环上具有取代基的苯基，其选自具有1至4个碳原子的烷基，具有1至4个碳原子的烷氧基，卤素原子，羟基 三氟甲基，硝基和氨基，2-吡啶基，3-吡啶基或4-吡啶基; R 3和R 4各自独立地为氢原子，具有1至6个碳原子的直链或支链烷基，具有1至4个碳原子的羟基烷基，具有3至8个碳原子的环烷基或苯基， 被替代 Y为碳原子数1〜12的亚烷基及其盐。