公开(公告)号：US08728884B1

公开(公告)日：2014-05-20

申请号：US12510687

申请日：2009-07-28

申请人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

发明人： Tahir Hussain ,  Miroslav Micovic ,  Wah S. Wong ,  Shawn D. Burnham

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462

摘要： A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.

摘要翻译： 一种制造具有源极和漏极的正常“关闭”GaN异质结构场效应晶体管的方法，包括沉积图案化以覆盖源极和漏极之间的沟道区域的钝化层，在钝化层中形成第一开口，第一开口 用于在所述沟道区域中限定栅极区域，并且所述第一开口沿着所述源极和漏极之间的电流流动的方向具有第一长度尺寸，以及将离子注入所述栅极区域内的注入区域中，其中所述植入区域具有第二 沿着电流流动方向的长度尺寸短于第一长度尺寸。

公开(公告)号：US08748244B1

公开(公告)日：2014-06-10

申请号：US13456421

申请日：2012-04-26

申请人： Andrea Corrion ,  Miroslav Micovic ,  Keisuke Shinohara ,  Peter J Willadsen ,  Shawn D Burnham ,  Hooman Kazemi ,  Paul B Hashimoto

发明人： Andrea Corrion ,  Miroslav Micovic ,  Keisuke Shinohara ,  Peter J Willadsen ,  Shawn D Burnham ,  Hooman Kazemi ,  Paul B Hashimoto

IPC分类号： H01L21/335

CPC分类号： H01L29/7787 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/66462

摘要： The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication method uses selective decomposition and selective regrowth of the Barrier layer and the Cap layer to engineer the bandgap of a region on a die to form an enhancement mode region. In these regions zero or more devices may be fabricated.

摘要翻译： 本发明涉及在相同裸片上分离10nm的增强模式和耗尽型高电位迁移率场效应晶体管的制造。 制造方法使用阻挡层和盖层的选择性分解和选择性再生长来设计管芯上的区域的带隙以形成增强模式区域。 在这些区域中，可以制造零个或多个器件。

公开(公告)号：US08686473B1

公开(公告)日：2014-04-01

申请号：US12792529

申请日：2010-06-02

申请人： Miroslav Micovic ,  Andrea Corrion ,  Keisuke Shinohara ,  Peter J Willadsen ,  Shawn D Burnham ,  Hooman Kazemi ,  Paul B Hashimoto

发明人： Miroslav Micovic ,  Andrea Corrion ,  Keisuke Shinohara ,  Peter J Willadsen ,  Shawn D Burnham ,  Hooman Kazemi ,  Paul B Hashimoto

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L31/102

CPC分类号： H01L29/66916 ,  H01L29/0891 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

摘要： The interface resistance between the source/drain and gate of an HFET may be significantly reduced by engineering the bandgap of the 2DEG outside a gate region such that the charge density is substantially increased. The resistance may be further reduced by using an n+GaN Cap layer over the channel layer and barrier layer such that a horizontal surface of the barrier layer beyond the gate region is covered by the n+GaN Cap layer. This technique is applicable to depletion and enhancement mode HFETs.

摘要翻译： 通过在栅极区域之外设计2DEG的带隙，使得电荷密度显着增加，可以显着降低HFET的源极/漏极和栅极之间的界面电阻。 通过在沟道层和阻挡层上使用n + GaN帽层可以进一步降低电阻，使得超过栅极区域的势垒层的水平表面被n + GaN帽层覆盖。 该技术适用于耗尽和增强型HFET。

公开(公告)号：US08383471B1

公开(公告)日：2013-02-26

申请号：US13083916

申请日：2011-04-11

申请人： Keisuke Shinihara ,  Andrea Corrion ,  Miroslav Micovic ,  Paul B. Hashimoto ,  Shawn D. Burnham ,  Hooman Kazemi ,  Peter J. Willadsen ,  Dean C. Regan

发明人： Keisuke Shinihara ,  Andrea Corrion ,  Miroslav Micovic ,  Paul B. Hashimoto ,  Shawn D. Burnham ,  Hooman Kazemi ,  Peter J. Willadsen ,  Dean C. Regan

IPC分类号： H01L21/338

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783

摘要： A method of fabricating a GaN HEMT includes growing a first epitaxial layer on a substrate, growing a second epitaxial layer on the first epitaxial layer, growing a third epitaxial layer on the second epitaxial layer, depositing a first dielectric film on the third epitaxial layer, using dielectric films to form a first sidewall dielectric spacer, forming a sidewall gate adjacent the first sidewall dielectric spacer. The sidewall gate may be made to be less than 50 nm in length.

摘要翻译： 制造GaN HEMT的方法包括在衬底上生长第一外延层，在第一外延层上生长第二外延层，在第二外延层上生长第三外延层，在第三外延层上沉积第一电介质膜， 使用介电膜形成第一侧壁电介质间隔件，形成邻近所述第一侧壁电介质间隔物的侧壁门。 侧壁浇口的长度可以小于50nm。

公开(公告)号：US08368119B1

公开(公告)日：2013-02-05

申请号：US13111771

申请日：2011-05-19

申请人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

发明人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/08 ,  H01L29/872

摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。

公开(公告)号：US06852615B2

公开(公告)日：2005-02-08

申请号：US10457506

申请日：2003-06-09

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Janna Ruth Duvall

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Janna Ruth Duvall

IPC分类号： H01L21/285 ,  H01L29/20 ,  H01L29/417 ,  H01L29/45 ,  H10L21/338

CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/41725 ,  Y10S438/975 ,  Y10S438/978

摘要： A process and related product in which ohmic contacts are formed in High Electron Mobility Transistors (HEMTs) employing compound substrates such as gallium nitride. An improved device and an improvement to a process for fabrication of ohmic contacts to GaN/AlGaN HEMTs using a novel two step resist process to fabricate the ohmic contacts are described. This novel two-step process consists of depositing a plurality of layers having compounds of Group III V elements on a substrate; patterning and depositing a first photoresist on one of the layers; etching recessed areas into this layer; depositing ohmic metals on the recessed areas; removing the first photoresist; patterning and depositing a second photoresist, smaller in profile than the first photoresist, on the layer; depositing more ohmic metal on the layer allowing for complete coverage of the recessed areas; removing the second photoresist, and annealing the semiconductor structure.

摘要翻译： 在使用诸如氮化镓的复合衬底的高电子迁移率晶体管（HEMT）中形成欧姆接触的工艺及相关产品。 描述了使用新颖的两步抗蚀剂工艺制造欧姆接触的改进的器件和用于制造对GaN / AlGaN HEMT的欧姆接触的工艺的改进。 这种新型的两步法包括在基片上沉积多层具有IIIV族元素化合物的层; 在其中一层上图案化和沉积第一光致抗蚀剂; 将凹陷区域蚀刻到该层中; 在凹陷区域沉积欧姆金属; 去除第一光致抗蚀剂; 在该层上图案化和沉积比第一光致抗蚀剂更小的第二光致抗蚀剂; 在该层上沉积更多的欧姆金属，允许完全覆盖凹陷区域; 去除第二光致抗蚀剂，并退火半导体结构。

公开(公告)号：US07470941B2

公开(公告)日：2008-12-30

申请号：US10313374

申请日：2002-12-06

申请人： Miroslav Micovic ,  Mike Antcliffe ,  Tahir Hussain ,  Paul Hashimoto

发明人： Miroslav Micovic ,  Mike Antcliffe ,  Tahir Hussain ,  Paul Hashimoto

IPC分类号： H01L31/0328

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

摘要翻译： 提出了一种用于制造异质结场效应晶体管（HFET）和一系列HFET层结构的方法。 在该方法中，执行将HFET半导体结构沉积到衬底上的步骤。 接下来，沉积光致抗蚀剂材料。 对应于源极和漏极焊盘对，去除部分光致抗蚀剂材料。 金属层沉积在结构上，形成源极焊盘和漏极焊盘对。 去除光致抗蚀剂材料，将其暴露于不同于源极和漏极焊盘对的区域中。 每个源极和漏极焊盘对具有相应的曝光区域。 该结构进行退火，并且器件是电隔离的。 蚀刻每个器件的暴露面积以形成栅极凹部，并且在凹部中形成栅极结构。 还提出了用于GaN / AlGaN HFET的半导体层结构。

公开(公告)号：US07989277B1

公开(公告)日：2011-08-02

申请号：US11853694

申请日：2007-09-11

申请人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

发明人： Louis Luh ,  Keh-Chung Wang ,  Wah S. Wong ,  Miroslav Micovic ,  David Chow ,  Don Hitko

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/08 ,  H01L29/872

摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.

摘要翻译： 公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。 使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。 还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。

公开(公告)号：US08030688B2

公开(公告)日：2011-10-04

申请号：US12486686

申请日：2009-06-17

申请人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

发明人： Tahir Hussain ,  Miroslav Micovic ,  Paul Hashimoto ,  Gary Peng ,  Ara K. Kurdoghlian

IPC分类号： H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/24 ,  H01L21/242 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66924

摘要： A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

摘要翻译： 说明了在随后的高温处理步骤中制造保护欧姆金属触点和器件通道的半导体器件的方法。 封装层用于覆盖通道和欧姆金属触点。 本发明提供一种其上沉积有多个半导体层的衬底。 半导体层用作器件的通道。 半导体层被封装层覆盖。 去除封装层和多个半导体层的一部分，其中沉积欧姆金属接触。 然后将欧姆金属触点退火以帮助降低它们的电阻。 封装层确保在退火步骤期间欧姆金属接触不迁移，并且该通道不会受退火步骤期间所需的高温的损害。

公开(公告)号：US07598131B1

公开(公告)日：2009-10-06

申请号：US12290921

申请日：2008-11-05

申请人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Mike Antcliffe

发明人： Miroslav Micovic ,  Tahir Hussain ,  Paul Hashimoto ,  Mike Antcliffe

IPC分类号： H01L21/338

CPC分类号： H01L29/66462 ,  H01L21/28575 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/7787

摘要： A method for fabricating heterojunction field effect transistors (HFET) and a family of HFET layer structures are presented. In the method, a step of depositing a HFET semiconductor structure onto a substrate is performed. Next, a photoresist material is deposited. Portions of the photoresist material are removed corresponding to source and drain pad pairs. A metal layer is deposited onto the structure, forming source pad and drain pad pairs. The photoresist material is removed, exposing the structure in areas other than the source and drain pad pairs. Each source and drain pad pair has a corresponding exposed area. The structure is annealed and devices are electrically isolated. The exposed area of each device is etched to form a gate recess and a gate structure is formed in the recess. Semiconductor layer structures for GaN/AlGaN HFETs are also presented.

摘要翻译： 提出了一种用于制造异质结场效应晶体管（HFET）和一系列HFET层结构的方法。 在该方法中，执行将HFET半导体结构沉积到衬底上的步骤。 接下来，沉积光致抗蚀剂材料。 对应于源极和漏极焊盘对，去除部分光致抗蚀剂材料。 金属层沉积在结构上，形成源极焊盘和漏极焊盘对。 去除光致抗蚀剂材料，将其暴露于不同于源极和漏极焊盘对的区域中。 每个源极和漏极焊盘对具有相应的曝光区域。 该结构进行退火，并且器件是电隔离的。 蚀刻每个器件的暴露面积以形成栅极凹部，并且在凹部中形成栅极结构。 还提出了用于GaN / AlGaN HFET的半导体层结构。