公开(公告)号：US20190131249A1

公开(公告)日：2019-05-02

申请号：US16231735

申请日：2018-12-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC: H01L23/544 ,  H01L23/528 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20180047703A1

公开(公告)日：2018-02-15

申请号：US15794277

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hsin WEI ,  Chi-Hsi WU ,  Chen-Hua YU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Wei-Ming CHEN

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H05K3/36 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H05K3/363

Abstract: Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.

公开(公告)号：US20180005955A1

公开(公告)日：2018-01-04

申请号：US15200747

申请日：2016-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L23/544 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/14 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/18 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure.

公开(公告)号：US20170005072A1

公开(公告)日：2017-01-05

申请号：US15003150

申请日：2016-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hsin WEI ,  Chi-Hsi WU ,  Chen-Hua YU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Wei-Ming CHEN

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L24/96 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/182

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Abstract translation: 提供了芯片封装的结构和形成方法。 芯片封装包括包括多个半导体管芯的芯片堆叠。 芯片封装还包括半导体芯片，并且半导体芯片高于芯片堆叠。 芯片封装还包括覆盖芯片堆叠的顶部和侧壁以及半导体芯片的侧壁的封装层。

公开(公告)号：US20170005071A1

公开(公告)日：2017-01-05

申请号：US14981458

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hsin WEI ,  Chi-Hsi WU ,  Chen-Hua YU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Wei-Ming CHEN

IPC: H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H05K3/363

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

Abstract translation: 提供了芯片封装的结构和形成方法。 芯片封装包括第一芯片结构和第二芯片结构。 第一芯片结构和第二芯片结构的高度是不同的。 芯片封装还包括覆盖第一芯片结构的侧壁和第二芯片结构的侧壁的封装层。 第一芯片结构和第二芯片结构的顶表面不被封装层覆盖。