公开(公告)号：US12191393B2

公开(公告)日：2025-01-07

申请号：US17239328

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Yen-Ru Lee ,  Chien-Chang Su ,  Chih-Yun Chin ,  Chien-Wei Lee ,  Pang-Yen Tsai ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

公开(公告)号：US12094761B2

公开(公告)日：2024-09-17

申请号：US18342855

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ru Lee ,  Chii-Horng Li ,  Chien-I Kuo ,  Li-Li Su ,  Chien-Chang Su ,  Heng-Wen Ting ,  Jung-Chi Tai ,  Che-Hui Lee ,  Ying-Wei Li

IPC: H01L21/82 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

公开(公告)号：US11367660B2

公开(公告)日：2022-06-21

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US09966469B2

公开(公告)日：2018-05-08

申请号：US15439035

申请日：2017-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Chien-Chang Su ,  Wang-Chun Huang ,  Yasutoshi Okuno

IPC: H01L21/8242 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/267 ,  H01L27/146

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1461 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

公开(公告)号：US09564321B2

公开(公告)日：2017-02-07

申请号：US13792261

申请日：2013-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Meng-Yueh Liu ,  Chien-Chang Su ,  Yuan-Feng Chao ,  Yuh-Da Fan

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02639 ,  H01L21/02656 ,  H01L21/3065

Abstract: A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature.

Abstract translation: 提供了循环沉积和蚀刻方法。 该方法包括在第一温度下在衬底上沉积外延层，并在高于第一温度的可变温度下蚀刻沉积的外延层的一部分。 在改变温度的同时进行蚀刻步骤。

公开(公告)号：US20220344516A1

公开(公告)日：2022-10-27

申请号：US17239328

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Ting Lin ,  Yen-Ru Lee ,  Chien-Chang Su ,  Chih-Yun Chin ,  Chien-Wei Lee ,  Pang-Yen Tsai ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

公开(公告)号：US20210265350A1

公开(公告)日：2021-08-26

申请号：US17128656

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yun Chin ,  Yen-Ru Lee ,  Chien-Chang Su ,  Yan-Ting Lin ,  Chien-Wei Lee ,  Bang-Ting Yan ,  Heng-Wen Ting ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess.

公开(公告)号：US20210098308A1

公开(公告)日：2021-04-01

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

公开(公告)号：US10326023B2

公开(公告)日：2019-06-18

申请号：US15972961

申请日：2018-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Chien-Chang Su ,  Wang-Chun Huang ,  Yasutoshi Okuno

IPC: H01L29/165 ,  H01L21/306 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L27/146 ,  H01L29/267

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

公开(公告)号：US09601626B2

公开(公告)日：2017-03-21

申请号：US14604537

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying Lee ,  Yasutoshi Okuno ,  Chien-Chang Su ,  Wang-Chun Huang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1461 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure protruding from a substrate and having a top face and a first side face and a second side face opposite to the first side face, and first semiconductor layers disposed over the first and second side faces of the fin structure. A thickness in a vertical direction of the first semiconductor layers is smaller than a height of the fin structure.