公开(公告)号：US20160322318A1

公开(公告)日：2016-11-03

申请号：US15207772

申请日：2016-07-12

申请人： EV GROUP E. THALLNER GMBH

发明人： Viorel Dragoi ,  Markus Wimplinger

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03015 ,  H01L2224/0311 ,  H01L2224/0355 ,  H01L2224/03848 ,  H01L2224/29 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29298 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00

摘要： A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

公开(公告)号：US08916972B2

公开(公告)日：2014-12-23

申请号：US13800653

申请日：2013-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Min-Chen Lin ,  Yi-Hang Lin

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/02321 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0355 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05187 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0541 ,  H01L2924/01029

摘要： An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure.

摘要翻译： 实施例集成电路结构包括衬底，衬底上的金属焊盘，在衬底上方的电子连接到金属焊盘的钝化后互连（PPI）结构，直接在PPI结构的顶表面上的薄氧化膜层 ，以及在薄氧化膜层和PPI结构上的聚合物层。

公开(公告)号：US20150279664A1

公开(公告)日：2015-10-01

申请号：US14670875

申请日：2015-03-27

申请人： Asia Pacific Microsystems, Inc.

发明人： Hung-Lin Yin

IPC分类号： H01L21/02 ,  H01L21/461 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L21/02255 ,  B81C1/00047 ,  B81C2201/019 ,  H01L21/02554 ,  H01L21/187 ,  H01L21/461 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/0355 ,  H01L2224/05551 ,  H01L2224/05638 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80894 ,  H01L2224/80896 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/80 ,  H01L2221/68381 ,  H01L21/306 ,  H01L2224/03

摘要： The present disclosure provides a method for fabricating semiconductor devices having high-precision gaps. The method includes steps of providing a first wafer; forming two or more regions having various ion dosage concentrations on a first surface of the first wafer; thermally oxidizing the first wafer so as to grow oxide layers with various thicknesses on the first surface of the first wafer; and bonding a second wafer to the thickest oxide layer of the first wafer so as to form one or more gaps.

摘要翻译： 本公开提供了一种制造具有高精度间隙的半导体器件的方法。 该方法包括提供第一晶片的步骤; 在所述第一晶片的第一表面上形成具有各种离子剂量浓度的两个或更多个区域; 热氧化第一晶片以在第一晶片的第一表面上生长具有各种厚度的氧化物层; 以及将第二晶片接合到所述第一晶片的最厚氧化物层，以形成一个或多个间隙。

公开(公告)号：US09130024B2

公开(公告)日：2015-09-08

申请号：US13417917

申请日：2012-03-12

申请人： Wen-Chih Chiou ,  David Ding-Chung Lu

发明人： Wen-Chih Chiou ,  David Ding-Chung Lu

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/30604 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/09 ,  H01L24/48 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/031 ,  H01L2224/0331 ,  H01L2224/0355 ,  H01L2224/05553 ,  H01L2224/08113 ,  H01L2224/08135 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

摘要翻译： 公开了一种使用冗余接合导体结构在多个半导体芯片之间进行层间电连接的三维半导体器件。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经被安装在第一芯片上方面向上或向下时，第一有效区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。

公开(公告)号：US12132016B2

公开(公告)日：2024-10-29

申请号：US18446028

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0355 ,  H01L2224/03612 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781 ,  H01L2224/27831 ,  H01L2224/29006 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/32225

摘要： A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US09698080B2

公开(公告)日：2017-07-04

申请号：US14846561

申请日：2015-09-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Chih Chiou ,  David Ding-Chung Lu

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/30604 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/09 ,  H01L24/48 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/031 ,  H01L2224/0331 ,  H01L2224/0355 ,  H01L2224/05553 ,  H01L2224/08113 ,  H01L2224/08135 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

公开(公告)号：US09478518B2

公开(公告)日：2016-10-25

申请号：US13637781

申请日：2011-02-23

申请人： Viorel Dragoi ,  Markus Wimplinger

发明人： Viorel Dragoi ,  Markus Wimplinger

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/03 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03015 ,  H01L2224/0311 ,  H01L2224/0355 ,  H01L2224/03848 ,  H01L2224/29 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29298 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00

摘要： A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

摘要翻译： 一种用于在第一基底的第一金属表面和第二基底的第二金属表面之间生产永久导电连接的方法，其中永久导电连接至少主要由金属之间的置换扩散 两个金属表面的离子和/或金属原子。

公开(公告)号：US20130040451A1

公开(公告)日：2013-02-14

申请号：US13637781

申请日：2011-02-23

申请人： Viorel Dragoi ,  Markus Wimplinger

发明人： Viorel Dragoi ,  Markus Wimplinger

IPC分类号： H01L21/28

CPC分类号： H01L24/03 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03015 ,  H01L2224/0311 ,  H01L2224/0355 ,  H01L2224/03848 ,  H01L2224/29 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29298 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00

摘要： A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces.

摘要翻译： 一种用于在第一基底的第一金属表面和第二基底的第二金属表面之间生产永久导电连接的方法，其中永久导电连接至少主要由金属之间的置换扩散 两个金属表面的离子和/或金属原子。

公开(公告)号：US08134235B2

公开(公告)日：2012-03-13

申请号：US11788974

申请日：2007-04-23

申请人： Wen-Chih Chiou ,  David Ding-Chung Lu

发明人： Wen-Chih Chiou ,  David Ding-Chung Lu

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/30604 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/09 ,  H01L24/48 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/031 ,  H01L2224/0331 ,  H01L2224/0355 ,  H01L2224/05553 ,  H01L2224/08113 ,  H01L2224/08135 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

摘要翻译： 一种使用冗余接合导体结构的三维半导体器件，用于在多个半导体芯片之间进行层间电连接。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经被安装在第一芯片上方面向上或向下时，第一有效区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。

公开(公告)号：US20070037337A1

公开(公告)日：2007-02-15

申请号：US11500717

申请日：2006-08-08

申请人： Hidekazu Takahashi ,  Eiji Sugiyama

发明人： Hidekazu Takahashi ,  Eiji Sugiyama

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2223/6677 ,  H01L2224/0332 ,  H01L2224/0355 ,  H01L2224/0391 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05173 ,  H01L2224/05178 ,  H01L2224/05179 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05188 ,  H01L2224/05339 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/32225 ,  H01L2224/83 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01054 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/13069 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device of the present invention is provided including the steps of forming a first conductive layer over a substrate; forming a second conductive layer containing a conductive particle and resin over the first conductive layer; and increasing an area where the first conductive layer and the second conductive layer are in contact with each other by irradiating the second conductive layer with a laser beam. By including the step of laser beam irradiation, the portion where the first conductive layer and the second conductive layer are in contact with each other can be increased and defective electrical connection between the first conductive layer and the second conductive layer can be improved.

摘要翻译： 提供本发明的半导体器件的制造方法，其特征在于包括：在基板上形成第一导电层的工序; 在所述第一导电层上形成包含导电粒子和树脂的第二导电层; 以及通过用激光束照射第二导电层来增加第一导电层和第二导电层彼此接触的面积。 通过包括激光束照射的步骤，可以增加第一导电层和第二导电层彼此接触的部分，并且可以提高第一导电层和第二导电层之间的有缺陷的电连接。