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公开(公告)号:US20230307375A1
公开(公告)日:2023-09-28
申请号:US18151583
申请日:2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hao-Cheng Hou , Tsung-Ding Wang , Jung Wei Cheng , Yu-Min Liang , Chien-Hsun Lee , Shang-Yun Hou , Wei-Yu Chen , Collin Jordon Fleshman , Kuo-Lung Pan , Shu-Rong Chun , Sheng-Chi Lin
CPC classification number: H01L23/5385 , H01L23/3121 , H01L24/19 , H01L24/20 , H01L25/50 , H10B80/00 , H01L25/18 , H01L21/561 , H01L23/481 , H01L23/562 , H01L2224/16227 , H01L24/16 , H01L24/29 , H01L2224/2929 , H01L2924/0665 , H01L2224/29386 , H01L2924/05442 , H01L2924/05432 , H01L2924/0503 , H01L24/32 , H01L2224/32225 , H01L24/73 , H01L2224/73204 , H01L2224/19 , H01L2224/211
Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.
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公开(公告)号:US20230307427A1
公开(公告)日:2023-09-28
申请号:US17806329
申请日:2022-06-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Chi Lin , Hao-Cheng Hou , Tsung-Ding Wang , Chien-Hsun Lee , Shang-Yun Hou
IPC: H01L23/31 , H01L23/00 , H01L23/498 , H01L25/18 , H01L23/538 , H01L21/48 , H01L25/10 , H01L25/00
CPC classification number: H01L25/105 , H01L21/4857 , H01L23/3121 , H01L23/49822 , H01L23/5381 , H01L23/5385 , H01L24/24 , H01L25/18 , H01L25/50 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/13025 , H01L2224/16227 , H01L2224/24227 , H01L2224/244 , H01L2224/25174 , H01L2224/32225 , H01L2224/73204 , H01L2225/1035 , H01L2225/1058
Abstract: A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.
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公开(公告)号:US20240105631A1
公开(公告)日:2024-03-28
申请号:US18152558
申请日:2023-01-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jeng-An Wang , Sheng-Chi Lin , Hao-Cheng Hou , Tsung-Ding Wang , Chien-Hsun Lee
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/31
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L2221/68372 , H01L2224/214
Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.
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