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公开(公告)号：US09659874B2
公开(公告)日：2017-05-23
申请号：US14883545
申请日：2015-10-14
发明人： Fu-Chiang Kuo , Ying-Hsun Chen , Shih-Chi Kuo , Tsung-Hsien Lee
IPC分类号： H01L29/06 , H01L23/544 , H01L21/308 , H01L21/306
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3081 , H01L21/3083 , H01L21/3085 , H01L21/762 , H01L21/78
摘要： A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.
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公开(公告)号：US09647022B2
公开(公告)日：2017-05-09
申请号：US14620460
申请日：2015-02-12
发明人： Tsai-Hao Hung , Han-Tang Lo , Shih-Chi Kuo , Tsung-Hsien Lee
IPC分类号： H01L21/266 , H01L21/761 , H01L21/265 , H01L27/146
CPC分类号： H01L27/1463 , H01L21/26533 , H01L21/266 , H01L21/761 , H01L27/1461 , H01L27/14614 , H01L27/14643 , H01L27/14689 , H01L2221/1026
摘要： The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers.
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公开(公告)号：US09257438B2
公开(公告)日：2016-02-09
申请号：US14158220
申请日：2014-01-17
发明人： Shih-Chi Kuo , Tsung-Hsien Lee , Ta-Ching Wei
IPC分类号： H01L21/70 , H01L27/11 , H01L21/311 , H01L21/3205 , H01L21/027
CPC分类号： H01L27/11 , H01L21/0271 , H01L21/0273 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32053 , H01L21/76205 , H01L21/76224 , H01L21/76819 , H01L21/76837 , H01L21/823437 , H01L21/823481 , H01L27/1116
摘要： In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.
摘要翻译： 根据一些实施例，提供半导体器件结构。 半导体器件结构包括衬底，并且衬底具有单元区域和逻辑区域。 半导体器件结构还包括形成在衬底中的隔离特征以及形成在隔离特征上和在单元区域处的第一栅极堆叠结构。 半导体器件结构还包括形成在隔离特征上和在单元区域处的第二栅极堆叠结构，并且第一栅极堆叠结构与第二栅极堆叠结构相邻。 第一栅极堆叠结构和第二栅极堆叠结构之间的隔离特征具有基本平坦的形貌。
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公开(公告)号：US11131541B2
公开(公告)日：2021-09-28
申请号：US16407799
申请日：2019-05-09
发明人： Shih-Yu Liao , Shih-Chi Kuo , Tsai-Hao Hung , Tsung-Hsien Lee
摘要： The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.
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公开(公告)号：US10508020B2
公开(公告)日：2019-12-17
申请号：US15411957
申请日：2017-01-20
发明人： Tsai-Hao Hung , Shih-Chi Kuo , Tsung-Hsien Lee , Tao-Cheng Liu
摘要： The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
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公开(公告)号：US09188547B2
公开(公告)日：2015-11-17
申请号：US14062802
申请日：2013-10-24
发明人： Chun-Yen Ho , Tsung-Hsien Lee , Han-Tang Lo
CPC分类号： G01N21/9501 , H01L22/12 , H01L22/20
摘要： A defect inspection apparatus is disclosed that includes a stage, a photosensitive element, and a controller. The stage can support a semiconductor element that has a plurality of complete dies and partial dies surrounding the complete dies. The photosensitive element is located above the stage. The controller is electrically connected to the photosensitive element to drive the photosensitive element to inspect the defects of the complete dies and the partial dies.
摘要翻译： 公开了一种缺陷检查装置，其包括台，感光元件和控制器。 该台可以支撑具有多个完整模具和围绕整个模具的部分模具的半导体元件。 感光元件位于舞台上方。 控制器电连接到感光元件以驱动感光元件来检查完整的模具和部分模具的缺陷。
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公开(公告)号：US09972771B2
公开(公告)日：2018-05-15
申请号：US15080569
申请日：2016-03-24
发明人： Chun-Chieh Mo , Shih-Chi Kuo , Tsung-Hsien Lee , Wu-An Weng , Chung-Yu Lin
摘要： MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.
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公开(公告)号：US09673200B2
公开(公告)日：2017-06-06
申请号：US15010798
申请日：2016-01-29
发明人： Shih-Chi Kuo , Tsung-Hsien Lee , Ta-Ching Wei
IPC分类号： H01L21/336 , H01L27/11 , H01L21/311 , H01L21/3205 , H01L21/027 , H01L21/768 , H01L21/762 , H01L21/8234
CPC分类号： H01L27/11 , H01L21/0271 , H01L21/0273 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32053 , H01L21/76205 , H01L21/76224 , H01L21/76819 , H01L21/76837 , H01L21/823437 , H01L21/823481 , H01L27/1116
摘要： A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.
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公开(公告)号：US20150116701A1
公开(公告)日：2015-04-30
申请号：US14062802
申请日：2013-10-24
发明人： Chun-Yen HO , Tsung-Hsien Lee , Han-Tang Lo
CPC分类号： G01N21/9501 , H01L22/12 , H01L22/20
摘要： A defect inspection apparatus is disclosed that includes a stage, a photosensitive element, and a controller. The stage can support a semiconductor element that has a plurality of complete dies and partial dies surrounding the complete dies. The photosensitive element is located above the stage. The controller is electrically connected to the photosensitive element to drive the photosensitive element to inspect the defects of the complete dies and the partial dies.
摘要翻译： 公开了一种缺陷检查装置，其包括台，感光元件和控制器。 该台可以支撑具有多个完整模具和围绕整个模具的部分模具的半导体元件。 感光元件位于舞台上方。 控制器电连接到感光元件以驱动感光元件来检查完整的模具和部分模具的缺陷。
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公开(公告)号：US20190035736A1
公开(公告)日：2019-01-31
申请号：US15904013
申请日：2018-02-23
发明人： Fu-Chiang KUO , Tao-Cheng Liu , Shih-Chi Kuo , Tsung-Hsien Lee
IPC分类号： H01L23/538 , H01L23/532 , H01L21/762 , H01L21/768
摘要： A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.
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