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公开(公告)号:US20210215550A1
公开(公告)日:2021-07-15
申请号:US17216047
申请日:2021-03-29
发明人: Tsai-Hao HUNG , Shih-Chi KUO
摘要: The structure of a micro-electro-mechanical system (MEMS) thermal sensor and a method of fabricating the MEMS thermal sensor are disclosed. A method of fabricating a MEMS thermal sensor includes forming first and second sensing electrodes with first and second electrode fingers, respectively, on a substrate and forming a patterned layer with a rectangular cross-section between a pair of the first electrode fingers. The first and second electrode fingers are formed in an interdigitated configuration and suspended above the substrate. The method further includes modifying the patterned layer to have a curved cross-section between the pair of the first electrode fingers, forming a curved sensing element on the modified patterned layer to couple to the pair of the first electrodes, and removing the modified patterned layer.
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公开(公告)号:US20200303542A1
公开(公告)日:2020-09-24
申请号:US16894644
申请日:2020-06-05
发明人: Chun-Chieh MO , Shih-Chi KUO
IPC分类号: H01L29/78 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/10 , H01L29/66 , H01L21/762
摘要: A semiconductor device includes: a first semiconductor region disposed over a second semiconductor region, wherein the first and second semiconductor regions have a first doping type and a second doping type, respectively; a first source/drain contact region and a second source/drain contact region having the second doping type and laterally spaced; and a gate electrode disposed laterally between the first and second source/drain contact regions, wherein the gate electrode comprises a first sidewall relatively closer to the first source/drain region and a second sidewall relatively closer to the second source/drain region, and wherein respective cross-sectional areas of the first and second sidewalls of the gate electrode are different from each other.
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公开(公告)号:US20200006093A1
公开(公告)日:2020-01-02
申请号:US16413275
申请日:2019-05-15
发明人: Chung-Yu LIN , Shih-Chi KUO , Chu-Chieh MO
IPC分类号: H01L21/67 , H01L21/02 , H01L21/687 , H01L21/673
摘要: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.
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公开(公告)号:US20200266346A1
公开(公告)日:2020-08-20
申请号:US16869340
申请日:2020-05-07
发明人: Chun-Chieh MO , Shih-Chi KUO
摘要: A memory cell includes: a resistive material layer comprising a first portion that extends along a first direction and a second portion that extends along a second direction, wherein the first and second directions are different from each other; a first electrode coupled to a bottom surface of the first portion of the resistive material layer; and a second electrode coupled to the second portion of the resistive material layer.
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公开(公告)号:US20200249397A1
公开(公告)日:2020-08-06
申请号:US16856581
申请日:2020-04-23
发明人: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC分类号: G02B6/136 , G02B6/122 , H01L21/308 , H01L21/306 , G02B5/18
摘要: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20200020377A1
公开(公告)日:2020-01-16
申请号:US16583029
申请日:2019-09-25
发明人: Chun-Chieh MO , Shih-Chi KUO
摘要: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.
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公开(公告)号:US20160163715A1
公开(公告)日:2016-06-09
申请号:US15010798
申请日:2016-01-29
发明人: Shih-Chi KUO , Tsung-Hsien LEE , Ta-Ching WEI
IPC分类号: H01L27/11 , H01L21/8234 , H01L21/027 , H01L21/762 , H01L21/311 , H01L21/3205
CPC分类号: H01L27/11 , H01L21/0271 , H01L21/0273 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32053 , H01L21/76205 , H01L21/76224 , H01L21/76819 , H01L21/76837 , H01L21/823437 , H01L21/823481 , H01L27/1116
摘要: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.
摘要翻译: 提供一种形成半导体器件结构的方法。 该方法包括在衬底上形成第一栅极堆叠结构和第二栅极堆叠结构,并且第一栅极堆叠结构包括邻近第二栅极堆叠结构的第一间隔物。 该方法还包括在第一栅极堆叠结构和第二栅极堆叠结构之间形成U形覆盖层,并且U形覆盖层的侧向侧壁与第一栅极堆叠结构的第一间隔物直接接触。 U形覆盖层的侧壁的顶部在第一栅极堆叠结构的第一间隔物的顶部的下方。
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公开(公告)号:US20240302591A1
公开(公告)日:2024-09-12
申请号:US18667981
申请日:2024-05-17
发明人: Tao-Cheng LIU , Tsai-Hao HUNG , Shih-Chi KUO
IPC分类号: G02B6/136 , G02B5/18 , G02B6/122 , H01L21/306 , H01L21/308
CPC分类号: G02B6/136 , G02B5/1819 , G02B5/1857 , G02B6/1225 , H01L21/30608 , H01L21/3086
摘要: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
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公开(公告)号:US20190237666A1
公开(公告)日:2019-08-01
申请号:US16378299
申请日:2019-04-08
发明人: Tsai-Hao HUNG , Shih-Chi KUO
CPC分类号: H01L45/1253 , G11C13/0007 , G11C2213/32 , H01L27/2436 , H01L45/085 , H01L45/1206 , H01L45/124 , H01L45/14 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1675
摘要: A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.
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公开(公告)号:US20190123269A1
公开(公告)日:2019-04-25
申请号:US15788690
申请日:2017-10-19
发明人: Chun-Chieh MO , Shih-Chi KUO
IPC分类号: H01L45/00
摘要: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.
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