公开(公告)号：US20170154891A1

公开(公告)日：2017-06-01

申请号：US15134262

申请日：2016-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Keng-Ying LIAO ,  Po-Zen CHEN ,  Yi-Jie CHEN ,  Yi-Hung CHEN

IPC: H01L27/115 ,  H01L21/311 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66825

Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

公开(公告)号：US20160062226A1

公开(公告)日：2016-03-03

申请号：US14471880

申请日：2014-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu LIN ,  Yi-Jie CHEN ,  Feng-Yuan CHIU ,  Ying-Chou CHENG ,  Kuei-Liang LU ,  Ya-Hui CHANG ,  Ru-Gun LIU ,  Tsai-Sheng GAU

IPC: G03F1/42 ,  G06F17/50 ,  G03F1/36

CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F7/038 ,  G06F17/5072

Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.

Abstract translation: 提供一种用于制造集成电路的光掩模和方法。 光掩模包括封闭在至少一个第一区域和至少一个第二区域中的多个主要特征，其中第一区域包括单个主要特征，而第二区域包括多个主要特征; 以及设置在第一区域和第二区域之间或第二区域之间的多个辅助特征。 光掩模提高了临界尺寸的精度，并有助于制造集成电路。

公开(公告)号：US20190115222A1

公开(公告)日：2019-04-18

申请号：US16219835

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Ying LIAO ,  Chung-Bin TSENG ,  Po-Zen CHEN ,  Yi-Hung CHEN ,  Yi-Jie CHEN

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308 ,  H01L21/28 ,  H01L21/033 ,  H01L21/027 ,  H01L29/66

CPC classification number: H01L21/3065 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

公开(公告)号：US20170160633A1

公开(公告)日：2017-06-08

申请号：US15436729

申请日：2017-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu LIN ,  Yi-Jie CHEN ,  Feng-Yuan CHIU ,  Ying-Chou CHENG ,  Kuei-Liang LU ,  Ya-Hui CHANG ,  Ru-Gun LIU ,  Tsai-Sheng GAU

IPC: G03F1/42 ,  G03F7/038 ,  G06F17/50 ,  G03F1/36

CPC classification number: G03F1/42 ,  G03F1/36 ,  G03F7/038 ,  G06F17/5072

Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.

公开(公告)号：US20170170024A1

公开(公告)日：2017-06-15

申请号：US15444039

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Keng-Ying LIAO ,  Chung-Bin TSENG ,  Po-Zen CHEN ,  Yi-Hung CHEN ,  Yi-Jie CHEN

IPC: H01L21/3065 ,  H01L29/66 ,  H01L21/28 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.