公开(公告)号：US20250062259A1

公开(公告)日：2025-02-20

申请号：US18450603

申请日：2023-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chao-Wen Shih ,  Kuo-Chiang Ting ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor device and methods of manufacture are discussed herein. A device includes a first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion resistant layer over the first semiconductor die, a bonding layer over the first thermal expansion resistant layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer.

公开(公告)号：US20240371822A1

公开(公告)日：2024-11-07

申请号：US18459171

申请日：2023-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Sheng Lin ,  Chao-Wen Shih ,  Kuo-Chiang Ting ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/66

Abstract: A method includes: forming first semiconductor dies in a first wafer, each die of the first semiconductor dies comprising: first active devices over a front-side of a first semiconductor substrate; performing first probe tests on the first wafer; based on the first probe tests, classifying each die of the first semiconductor dies as a first good die, a first marginal die, or a first bad die; forming second semiconductor dies in a second wafer; performing second probe tests on the second wafer; based on the second probe tests, classifying each die of the second semiconductor dies as a second good die, a second marginal die, or a second bad die; and bonding the second wafer to the first wafer, each die of the first semiconductor dies aligning with a corresponding die of the second semiconductor dies.

公开(公告)号：US20240153881A1

公开(公告)日：2024-05-09

申请号：US18402061

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tzuan-Horng Liu ,  Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.

公开(公告)号：US20240021509A1

公开(公告)日：2024-01-18

申请号：US18358570

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76846

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US11749626B2

公开(公告)日：2023-09-05

申请号：US17222249

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chung-Shi Liu ,  Shou Zen Chang ,  Chao-Wen Shih

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L21/78 ,  H01L23/552 ,  H01L25/10 ,  H01L25/00 ,  H01P3/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01L23/31 ,  H01Q9/04 ,  H01L21/683 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01P3/003 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q9/0457 ,  H01L21/486 ,  H01L2221/68331 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3025 ,  H01Q21/065

Abstract: An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

公开(公告)号：US11587894B2

公开(公告)日：2023-02-21

申请号：US16924216

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Tzuan-Horng Liu ,  Jen-Li Hu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/64

Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.

公开(公告)号：US11245176B2

公开(公告)日：2022-02-08

申请号：US16740464

申请日：2020-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Chien Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01L23/498 ,  H01Q1/22 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q19/06 ,  H01Q25/00 ,  H01L21/683 ,  H01Q21/06 ,  H01Q21/29

Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

公开(公告)号：US20210288030A1

公开(公告)日：2021-09-16

申请号：US17334025

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Tzuan-Horng Liu ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Nien-Fang Wu

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/544 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/78 ,  H01L21/683 ,  H01L23/48

Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

公开(公告)号：US11043731B2

公开(公告)日：2021-06-22

申请号：US16671182

申请日：2019-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nan-Chin Chuang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chao-Wen Shih ,  Shou-Zen Chang

IPC: H01Q1/22 ,  H01Q21/00 ,  H01Q19/30 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01Q21/24 ,  H01L23/31 ,  H01Q1/52 ,  H01Q15/14 ,  H01Q21/28

Abstract: A package structure including a first redistribution circuit structure, a semiconductor die, first antennas and second antennas is provided. The semiconductor die is located on and electrically connected to the first redistribution circuit structure. The first antennas and the second antennas are located over the first redistribution circuit structure and electrically connected to the semiconductor die through the first redistribution circuit structure. A first group of the first antennas are located at a first position, a first group of the second antennas are located at a second position, and the first position is different from the second position in a stacking direction of the first redistribution circuit structure and the semiconductor die.

公开(公告)号：US11004809B2

公开(公告)日：2021-05-11

申请号：US16426365

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Ping Chiang ,  Yi-Che Chiang ,  Nien-Fang Wu ,  Min-Chien Hsiao ,  Chao-Wen Shih ,  Shou-Zen Chang ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00 ,  H01L21/56 ,  H01L23/538 ,  H01Q1/22 ,  H01Q21/22

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.