公开(公告)号：US20240413150A1

公开(公告)日：2024-12-12

申请号：US18790013

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company , Ltd.

Inventor： Chieh-Ping Wang ,  Tai-Chun Huang ,  Yung-Cheng Lu ,  Ting-Gang Chen ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H10B99/00

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

公开(公告)号：US12087641B2

公开(公告)日：2024-09-10

申请号：US17237249

申请日：2021-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chung-Ting Ko ,  Wen-Ju Chen ,  Tai-Chun Huang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/0259 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.

公开(公告)号：US11835760B1

公开(公告)日：2023-12-05

申请号：US17843940

申请日：2022-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Chun Huang ,  Lan-Chou Cho ,  Chewn-Pu Jou ,  Stefan Rusu

IPC: G02B6/12

CPC classification number: G02B6/12026 ,  G02B6/12016

Abstract: The present disclosure provides a calibration system for wavelength-division multiplexing (WDM), a WDM system, and a calibrating method for WDM. The calibration system includes heating devices, an optical sensor, and an electrical device. When the optical sensor receives no beam with energy exceeding a threshold value from a first channel, the optical sensor transmits a first signal to the electrical device. In response to the first signal, the electrical device is configured to control the one or more of the heating devices to heat one or more of channels. When the optical sensor receives a beam having energy exceeding the threshold value from the first channel, the optical sensor transmits a second signal to the electrical device. In response to the second signal, the electrical device is configured to control the one or more of the heating devices to maintain the temperature of the one or more of the channels.

公开(公告)号：US11532479B2

公开(公告)日：2022-12-20

申请号：US16837607

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Gang Chen ,  Wan-Hsien Lin ,  Chieh-Ping Wang ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/764 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

公开(公告)号：US10714620B2

公开(公告)日：2020-07-14

申请号：US16229118

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US20190181247A1

公开(公告)日：2019-06-13

申请号：US16278434

申请日：2019-02-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L21/033 ,  C23C16/455 ,  C23C16/34 ,  C23C16/30

Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.

公开(公告)号：US20190088499A1

公开(公告)日：2019-03-21

申请号：US16179607

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Jie Huang ,  Syun-Ming Jang ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tai-Chun Huang ,  Chunyao Wang ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/49 ,  H01L29/10 ,  H01L29/78 ,  H01L21/28

Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.

公开(公告)号：US10164114B2

公开(公告)日：2018-12-25

申请号：US15991680

申请日：2018-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Tai-Chun Huang ,  Tien-I Bao

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033

Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.

公开(公告)号：US10157997B2

公开(公告)日：2018-12-18

申请号：US15667491

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bor Chiuan Hsieh ,  Chung-Ting Ko ,  Ting-Gang Chen ,  Chien Chung Huang ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L29/66

Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.

公开(公告)号：US20180151699A1

公开(公告)日：2018-05-31

申请号：US15404772

申请日：2017-01-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Cyuan Lu ,  Tai-Chun Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L29/66795 ,  C23C16/30 ,  C23C16/345 ,  C23C16/45525 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.