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    MEMORY CELL
    1.
    发明公开
    MEMORY CELL 审中-公开

    公开(公告)号：US20240087646A1

    公开(公告)日：2024-03-14

    申请号：US18167437

    申请日：2023-02-10

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon-Jhy Liaw

    IPC分类号： G11C15/04 ,  G11C7/18 ,  H03K19/017

    CPC分类号： G11C15/04 ,  G11C7/18 ,  H03K19/01742

    摘要： Memory cells are provided. A memory cell includes a first data storage cell, a second data storage cell and a match cell. The first data storage cell includes a first pull-down transistor, a first pull-up transistor and a first pass-gate transistor. The second data storage cell includes a second pull-down transistor, a second pull-up transistor, and a second pass-gate transistor. The match cell includes a first data transistor and a second data transistor. The first data transistor is electrically connected to the first pull-down transistor, the first pull-up transistor and the first pass-gate transistor. The second data transistor is electrically connected to the second pull-down transistor, the second pull-up transistor and the second pass-gate transistor. The first and second data storage cells and the match cell have the same cell height. The match cell is disposed between the first and second data storage cells.

    SRAM structure and method for manufacturing SRAM structure
    2.
    发明授权
    SRAM structure and method for manufacturing SRAM structure 有权

    公开(公告)号：US11276696B2

    公开(公告)日：2022-03-15

    申请号：US17079863

    申请日：2020-10-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chih-Hung Hsieh ,  Yu-Min Liao ,  Jhon-Jhy Liaw

    IPC分类号： H01L27/11 ,  G11C11/41 ,  G11C11/412 ,  G11C11/40

    摘要： A SRAM structure includes a first SRAM cell, a second SRAM cell arranged in mirror symmetry with the first SRAM cell along a first direction, a third SRAM cell arranged in mirror symmetry with the first SRAM cell along a second direction perpendicular to the first direction, and a fourth SRAM cell arranged in mirror symmetry with the third SRAM cell along the first direction and arranged in mirror symmetry with the second SRAM cell along the second direction. Each of SRAM cells includes a first and a second pull-down transistor. The SRAM structure further includes a contact bar extending in the second direction to sources of the second pull-down transistors of the first and third SRAM cells and extending in a third direction opposite to the second direction to sources of the second pull-down transistors of the second and fourth SRAM cells.

    Apparatus for FinFETs
    3.
    发明授权
    Apparatus for FinFETs 有权

    公开(公告)号：US10068905B2

    公开(公告)日：2018-09-04

    申请号：US15178045

    申请日：2016-06-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon-Jhy Liaw

    IPC分类号： H01L27/088 ,  H01L21/8244 ,  H01L21/70 ,  H01L27/092 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

    摘要： A device comprises a first inverter comprising a first p-type transistor (PU) and a first n-type transistor (PD), a second inverter cross-coupled to the first inverter comprising a second PU and a second PD, a first pass-gate transistor coupled between the first inverter and a first bit line and a second pass-gate transistor coupled between the second inverter and a second bit line, wherein at least one transistor has a two-stage fin structure, and wherein a width of a bottom portion of the two-stage fin structure is greater than a width of an upper portion of the two-stage fin structure.

    SRAM cell comprising FinFETs
    8.
    发明授权
    SRAM cell comprising FinFETs 有权
    SRAM单元包括FinFET

    公开(公告)号：US08830732B2

    公开(公告)日：2014-09-09

    申请号：US13691373

    申请日：2012-11-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon-Jhy Liaw

    IPC分类号： G11C11/00 ,  G11C11/412 ,  H01L27/088

    CPC分类号： G11C11/412 ,  H01L27/0886 ,  H01L27/1108

    摘要： A Static Random Access Memory (SRAM) cell includes a first long boundary and a second long boundary parallel to a first direction, and a first short boundary and a second short boundary parallel to a second direction perpendicular to the first direction. The first and the second long boundaries are longer than, and form a rectangle with, the first and the second short boundaries. A CVss line carrying a VSS power supply voltage crosses the first long boundary and the second long boundary. The CVss line is parallel to the second direction. A bit-line and a bit-line bar are on opposite sides of the CVss line. The bit-line and the bit-line bar are configured to carry complementary bit-line signals.

    摘要翻译： 静态随机存取存储器（SRAM）单元包括平行于第一方向的第一长边界和第二长边界，以及平行于垂直于第一方向的第二方向的第一短边界和第二短边界。 第一和第二长边界比第一和第二短边界长，并形成一个矩形。 承载VSS电源电压的CVss线跨越第一长边界和第二长边界。 CVss线平行于第二个方向。 位线和位线条位于CVss线的两侧。 位线和位线条配置为携带互补的位线信号。

    Contact Plugs in SRAM Cells and the Method of Forming the Same
    9.
    发明申请
    Contact Plugs in SRAM Cells and the Method of Forming the Same 有权
    SRAM单元中的接触插头及其形成方法

    公开(公告)号：US20140151812A1

    公开(公告)日：2014-06-05

    申请号：US13691367

    申请日：2012-11-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon-Jhy Liaw

    IPC分类号： H01L21/768 ,  H01L23/498

    CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/1108 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes forming a dielectric layer over a portion of an SRAM cell. The SRAM cell includes a first pull-up transistor and a second pull-up transistor, a first pull-down transistor and a second pull-down transistor forming cross-latched inverters with the first pull-up transistor and the second pull-up transistor, and a first pass-gate transistor and a second pass-gate transistor connected to drains of the first pull-up transistor and the first pull-down transistor and drains of the second pull-up transistor and the second pull-down transistor, respectively. A first mask layer is formed over the dielectric layer and patterned. A second mask layer is formed over the dielectric layer and patterned. The dielectric layer is etched using the first mask layer and the second mask layer in combination as an etching mask, wherein a contact opening is formed in the dielectric layer. A contact plug is formed in the contact opening.

    摘要翻译： 一种方法包括在SRAM单元的一部分上形成电介质层。 SRAM单元包括第一上拉晶体管和第二上拉晶体管，第一下拉晶体管和第二下拉晶体管，其与第一上拉晶体管和第二上拉晶体管形成交叉锁存的反相器 以及分别连接到第一上拉晶体管和第一下拉晶体管的漏极以及第二上拉晶体管和第二下拉晶体管的漏极的第一通过栅晶体管和第二通过栅极晶体管 。 在电介质层上形成第一掩模层并进行图案化。 第二掩模层形成在电介质层上并被图案化。 使用第一掩模层和第二掩模层作为蚀刻掩模来蚀刻电介质层，其中在电介质层中形成接触开口。 接触插塞形成在接触开口中。