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    Method and structure for CMOS-MEMS thin film encapsulation
    4.
    发明授权
    Method and structure for CMOS-MEMS thin film encapsulation 有权

    公开(公告)号：US10689247B2

    公开(公告)日：2020-06-23

    申请号：US15860357

    申请日：2018-01-02

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Chia Liu ,  Chia-Hua Chu ,  Chun-Wen Cheng

    IPC: B81B7/00 ,  B81C1/00

    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

    Vacuum sealed MEMS and CMOS package
    7.
    发明授权
    Vacuum sealed MEMS and CMOS package 有权

    公开(公告)号：US10155659B2

    公开(公告)日：2018-12-18

    申请号：US15722214

    申请日：2017-10-02

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chun-Wen Cheng ,  Yi-Chuan Teng ,  Hung-Chia Tsai ,  Chia-Hua Chu

    IPC: B81B7/00 ,  B81C1/00 ,  H01L21/768

    Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.

    Stacked Semiconductor Structure and Method of Forming the Same
    9.
    发明申请
    Stacked Semiconductor Structure and Method of Forming the Same 审中-公开

    公开(公告)号：US20180265351A1

    公开(公告)日：2018-09-20

    申请号：US15984610

    申请日：2018-05-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

    IPC: B81C1/00

    CPC classification number: B81C1/00238 ,  B81C2203/0792

    Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.

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