METHOD FOR ENHANCING TUNNEL MAGNETORESISTANCE IN MEMORY DEVICE

    公开(公告)号:US20210249062A1

    公开(公告)日:2021-08-12

    申请号:US17243612

    申请日:2021-04-29

    IPC分类号: G11C11/16

    摘要: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

    Memory device and method of operating same

    公开(公告)号:US09875774B1

    公开(公告)日:2018-01-23

    申请号:US15460687

    申请日:2017-03-16

    IPC分类号: G11C7/08 G11C5/06 G11C7/10

    摘要: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller. The controller is configured to: permit, during a recovery phase in which a gleaned amount of charge (gleaned charge) is recovered, flow of charge (charge-flow) between the recycling arrangement and the branched line; interrupt, during a drainage phase in which the gleaned charge is preserved, charge-flow between the recycling arrangement and the branched line; and permit, during a reuse phase in which the gleaned charge is reused, charge-flow between the recycling arrangement and the branched line.

    METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN

    公开(公告)号:US20220328124A1

    公开(公告)日:2022-10-13

    申请号:US17848416

    申请日:2022-06-24

    发明人: Hung-Chang Yu

    摘要: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.

    Circuit and method to enhance efficiency of memory

    公开(公告)号:US10950658B2

    公开(公告)日:2021-03-16

    申请号:US16245857

    申请日:2019-01-11

    发明人: Hung-Chang Yu

    摘要: A circuit includes: a first node to receive a first current; a first resistive element receiving a first branch current of the first current; first transistors each including a first terminal connected to the second end of the first resistive element; a second resistive element connected to the first node and receiving a second branch current of the first current; a second node to receive a second current; a second transistor including a first terminal, the first terminal of the second transistor connected to the second node and receiving a first branch current of the second current; a third resistive element connected to the second node and receiving a second branch current of the second current; wherein a temperature coefficient is adjusted by a resistance of the second resistive element and a resistance of the third resistive element and corresponding to the first current.

    Memory device and method of operating same

    公开(公告)号:US10147469B2

    公开(公告)日:2018-12-04

    申请号:US15877034

    申请日:2018-01-22

    摘要: A semiconductor device including: a sense amplifier; a branched line selectively connectable to the amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.

    Sensing circuit with reduced bias clamp

    公开(公告)号:US09673799B2

    公开(公告)日:2017-06-06

    申请号:US14942372

    申请日:2015-11-16

    IPC分类号: H03K5/24 G11C7/06 G11C13/00

    摘要: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

    Sample-and-Hold Current Sense Amplifier and Related Method
    7.
    发明申请
    Sample-and-Hold Current Sense Amplifier and Related Method 有权
    采样保持电流检测放大器及相关方法

    公开(公告)号:US20150063048A1

    公开(公告)日:2015-03-05

    申请号:US14016917

    申请日:2013-09-03

    IPC分类号: H03F3/45 G11C7/06

    摘要: A device includes an amplifier and a first switched current sampler. The first switched current sampler includes a first transistor, a first capacitor, and first, second, and third switches. The first capacitor has a first terminal electrically connected to a gate electrode of the first transistor, and a second terminal electrically connected to a source electrode of the first transistor. The first switch has a first terminal electrically connected to a first current source, and a second terminal electrically connected to the gate electrode of the first transistor. The second switch has a first terminal electrically connected to the first current source, and a second terminal electrically connected to a drain electrode of the first transistor. The third switch has a first terminal electrically connected to the drain electrode of the first transistor, and a second terminal electrically connected to a first input terminal of the amplifier.

    摘要翻译: 器件包括放大器和第一开关电流采样器。 第一开关电流采样器包括第一晶体管,第一电容器以及第一,第二和第三开关。 第一电容器具有电连接到第一晶体管的栅电极的第一端子和与第一晶体管的源电极电连接的第二端子。 第一开关具有电连接到第一电流源的第一端子和电连接到第一晶体管的栅电极的第二端子。 第二开关具有电连接到第一电流源的第一端子和与第一晶体管的漏电极电连接的第二端子。 第三开关具有电连接到第一晶体管的漏电极的第一端子和与放大器的第一输入端子电连接的第二端子。

    Memory device with recycling arrangement for gleaned charge

    公开(公告)号:US11031051B2

    公开(公告)日:2021-06-08

    申请号:US16698552

    申请日:2019-11-27

    摘要: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of memory cells; an array of bit lines connected to corresponding memory cells in the array of memory cells; a multiplexer configured to selectively connect the branched line to a selected one in the array of memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.