公开(公告)号：US20240347439A1

公开(公告)日：2024-10-17

申请号：US18753091

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311

摘要： A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.

公开(公告)号：US20220310468A1

公开(公告)日：2022-09-29

申请号：US17838434

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Liang LIN ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Yi-Wen WU ,  Techi WONG ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L21/48

摘要： A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

公开(公告)号：US20230207476A1

公开(公告)日：2023-06-29

申请号：US18177921

申请日：2023-03-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/5386 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/16 ,  H01L21/568 ,  H01L24/92 ,  H01L24/73 ,  H01L2224/92225 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2224/73253

摘要： A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

公开(公告)号：US20220367399A1

公开(公告)日：2022-11-17

申请号：US17411701

申请日：2021-08-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Meng-Liang LIN ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

公开(公告)号：US20210384125A1

公开(公告)日：2021-12-09

申请号：US17405389

申请日：2021-08-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

摘要： A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.

公开(公告)号：US20210242122A1

公开(公告)日：2021-08-05

申请号：US17233852

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

公开(公告)号：US20240203893A1

公开(公告)日：2024-06-20

申请号：US18589513

申请日：2024-02-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Meng-Liang LIN ,  Po-Yao CHUANG ,  Techi WONG ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L25/18 ,  H01L25/50

摘要： A package structure is provided, which includes a redistribution structure, an interposer substrate disposed over the redistribution structure, a first semiconductor die disposed between the redistribution structure and the interposer substrate, a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface of the redistribution structure, and a first protective layer surrounding the first semiconductor die.

公开(公告)号：US20210320069A1

公开(公告)日：2021-10-14

申请号：US17358987

申请日：2021-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Techi WONG

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/16 ,  H01L21/683

摘要： Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.

公开(公告)号：US20240363533A1

公开(公告)日：2024-10-31

申请号：US18769153

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L23/5283 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/3207 ,  H01L2224/32225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/1436 ,  H01L2924/1437

摘要： A package structure is provided. The package structure includes a first interconnect structure, a die structure over the first interconnect structure, and a dam structure on the die structure. The package structure also includes a second interconnect structure over the die structure and the dam structure. The package structure further includes a ring structure over the first interconnect structure and surrounding the die structure and the dam structure. In addition, the package structure includes a plurality of connectors electrically connected to the first interconnect structure and the second interconnect structure. A top surface of the ring structure is higher than a top surface of the first interconnect structure and lower than a top surface of each of the plurality of connectors.

公开(公告)号：US20240071909A1

公开(公告)日：2024-02-29

申请号：US18502307

申请日：2023-11-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Wen WU ,  Techi WONG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Shih-Ting HUNG ,  Shin-Puu JENG

IPC分类号： H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/73203

摘要： A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.