公开(公告)号：US11004847B2

公开(公告)日：2021-05-11

申请号：US16684929

申请日：2019-11-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06

摘要： An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

公开(公告)号：US09935011B2

公开(公告)日：2018-04-03

申请号：US14851535

申请日：2015-09-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

公开(公告)号：US09847332B2

公开(公告)日：2017-12-19

申请号：US15263593

申请日：2016-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L21/336 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC分类号： H01L27/0921 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

摘要： The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

公开(公告)号：US20160379978A1

公开(公告)日：2016-12-29

申请号：US15263593

申请日：2016-09-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng CHING ,  Ting-Hung Hsu

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L27/0921 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

摘要： The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

摘要翻译： 本公开提供了一种用于制造集成电路器件的方法。 该方法包括提供包括具有第一和第二金属氧化物半导体（MOS）区域的衬底的前体。 第一和第二MOS区域分别包括第一和第二栅极区域，半导体层堆叠和源极/漏极区域。 该方法还包括横向曝光和氧化第一栅极区域中的半导体层堆叠以形成第一外部氧化物层和内部纳米线组，并且暴露第一内部纳米线组。 第一个高k /金属门（HK / MG）堆叠绕第一个内部纳米线组。 该方法还包括横向曝光和氧化第二栅极区域中的半导体层堆叠以形成第二外部氧化物层和内部纳米线组，并暴露第二个内部纳米线组。 第二个HK / MG堆叠绕第二个内部纳米线集合。

公开(公告)号：US09443856B2

公开(公告)日：2016-09-13

申请号：US14918223

申请日：2015-10-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L27/088 ,  H01L29/775 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC分类号： H01L27/0921 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

摘要： The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

公开(公告)号：US09153668B2

公开(公告)日：2015-10-06

申请号：US13901399

申请日：2013-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Guan-Lin Chen ,  Ting-Hung Hsu ,  Jiun-Jia Huang

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/02356 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

摘要翻译： 提供了具有可调拉伸应变的翅片场效应晶体管（FinFET）和调整集成电路中的拉伸应变的实施例方法。 该方法包括在鳍片的栅极区域的相对侧上形成源极/漏极区域，在鳍片上形成间隔物，邻近源极/漏极区域的间隔物，在间隔物之间​​沉积电介质; 并且执行退火处理以使电介质收缩，电介质收缩使间隔物变形，间隔件变形扩大了翅片中的栅极区域。

公开(公告)号：US09035277B2

公开(公告)日：2015-05-19

申请号：US13957102

申请日：2013-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L29/06 ,  H01L29/76 ,  H01L27/12 ,  H01L21/00 ,  H01L21/31 ,  H01L21/84 ,  H01L29/423

CPC分类号： H01L27/092 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： The present disclosure provides a method for fabricating an integrated circuit (IC) device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, source/drain regions and isolation regions. The method includes exposing and oxidizing the first semiconductor layer stack to form a first outer oxide layer and a first inner nanowire, and removing the first outer oxide layer to expose the first inner nanowire in the first gate region. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire. The method includes exposing and oxidizing the second semiconductor layer stack to form second outer oxide layer and inner nanowire, and removing the second outer oxide layer to expose the second inner nanowire in the second gate region. A second HK/MG stack wraps around the second inner nanowire.

摘要翻译： 本公开提供了一种用于制造集成电路（IC）装置的方法。 该方法包括提供包括具有第一和第二金属氧化物半导体（MOS）区域的衬底的前体。 第一和第二MOS区域包括第一和第二栅极区域，半导体层堆叠，源极/漏极区域和隔离区域。 该方法包括曝光和氧化第一半导体层堆叠以形成第一外部氧化物层和第一内部纳米线，以及去除第一外部氧化物层以暴露第一栅极区域中的第一内部纳米线。 第一个高k /金属门（HK / MG）堆叠缠绕在第一个内部纳米线周围。 该方法包括曝光和氧化第二半导体层堆叠以形成第二外部氧化物层和内部纳米线，以及去除第二外部氧化物层以暴露第二栅极区域中的第二内部纳米线。 第二个HK / MG堆叠环绕第二个内部纳米线。

公开(公告)号：US20210265343A1

公开(公告)日：2021-08-26

申请号：US17315926

申请日：2021-05-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

摘要： An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

公开(公告)号：US20170309629A1

公开(公告)日：2017-10-26

申请号：US15645352

申请日：2017-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Ting-Hung Hsu

IPC分类号： H01L27/092 ,  H01L29/775 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06

摘要： An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.

公开(公告)号：US20160056157A1

公开(公告)日：2016-02-25

申请号：US14839560

申请日：2015-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Guan-Lin Chen ,  Ting-Hung Hsu ,  Jiun-Jia Huang

IPC分类号： H01L27/092 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/02356 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

摘要： A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.

摘要翻译： 提供了具有可调拉伸应变的翅片场效应晶体管（FinFET）和调整集成电路中的拉伸应变的实施例方法。 该方法包括在鳍片的栅极区域的相对侧上形成源极/漏极区域，在鳍片上形成间隔物，邻近源极/漏极区域的间隔物，在间隔物之间​​沉积电介质; 并且执行退火处理以使电介质收缩，电介质收缩使间隔物变形，间隔件变形扩大了翅片中的栅极区域。