公开(公告)号：US5917766A

公开(公告)日：1999-06-29

申请号：US978594

申请日：1997-11-26

申请人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

发明人： Takaharu Tsuji ,  Mikio Asakura ,  Tadaaki Yamauchi ,  Koji Tanaka

IPC分类号： G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/34 ,  G11C29/50 ,  G11C11/401

摘要： A semiconductor memory device that operates in various modes such as in a normal operation mode and a disturb accelerated test mode in which two word lines are activated simultaneously, includes a boosting power supply circuit, a boosted voltage supply line, and an input terminal connected to the boosted voltage supply line. In a disturb accelerated test mode or in a burn-in test mode, an external voltage is supplied from an external power supply to the input terminal. A word line is reliably boosted in voltage in a disturb accelerated test mode.

摘要翻译： 一种半导体存储器件，其工作在诸如正常操作模式和同时激活两个字线的干扰加速测试模式的各种模式中，包括升压电源电路，升压电源线​​和连接到 升压电源线​​。 在干扰加速测试模式或老化测试模式下，外部电源从外部电源提供给输入端。 在干扰加速测试模式下，字线可靠地升高电压。

公开(公告)号：US5812492A

公开(公告)日：1998-09-22

申请号：US781013

申请日：1997-01-10

申请人： Tadaaki Yamauchi ,  Takaharu Tsuji ,  Mikio Asakura

发明人： Tadaaki Yamauchi ,  Takaharu Tsuji ,  Mikio Asakura

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/1045

摘要： A semiconductor memory device operates switched between a first readout mode in which data readout according to a specified activation of a column address strobe signal /CAS that shows a transition in synchronization with an external clock signal is output during a period including the specified activation of signal /CAS, and a second readout mode in which the readout data is output during a subsequent predetermined period of signal /CAS. A control circuit for controlling the data output timing from an output buffer activates the output buffer at an elapse of a predetermined time following the specified activation of signal /CAS in the first readout mode. In the second readout mode, the control circuit activates the output buffer according to activation of signal /CAS at a predetermined period.

摘要翻译： 半导体存储器件在第一读出模式之间切换，在第一读出模式中，在包括指定的信号激活的时段期间输出其中根据指示的激活表示与外部时钟信号同步的转换的列地址选通信号/ CAS的数据读出 / CAS，以及在信号/ CAS的后续预定周期期间输出读出数据的第二读出模式。 用于从输出缓冲器控制数据输出定时的控制电路在第一读出模式中指定的信号/ CAS激活之后经过预定时间激活输出缓冲器。 在第二读出模式中，控制电路根据信号/ CAS在预定周期的激活来激活输出缓冲器。

公开(公告)号：US5978299A

公开(公告)日：1999-11-02

申请号：US222793

申请日：1998-12-30

申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/34

CPC分类号： G11C5/147

摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

公开(公告)号：US6003148A

公开(公告)日：1999-12-14

申请号：US781387

申请日：1997-01-13

申请人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

发明人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34 ,  G06F11/00

CPC分类号： G11C29/34

摘要： In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

摘要翻译： 在预定的多位测试模式中，多位测试电路114将确定结果数据对RDM0和/ RDM0发送到RDM3和/ RDM3，每个RDM3和/ RDM3对应于从由一列选择线选择的存储器单元读取的数据的逻辑的匹配/不匹配 相应的一个存储单元平面块。 在每个存储单元平面块中，由单个列选择行选择的存储单元列可以被替换为单元。 根据确定结果数据RDM0和/ RDM0至RDM3和/ RDM3来替换包含有缺陷存储单元的存储单元列的单位。

公开(公告)号：US5732034A

公开(公告)日：1998-03-24

申请号：US759200

申请日：1996-12-04

申请人： Mikio Asakura ,  Tadaaki Yamauchi ,  Takashi Ito

发明人： Mikio Asakura ,  Tadaaki Yamauchi ,  Takashi Ito

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C8/06

摘要： An input first stage is used for inputting both addresses and address keys. A test mode setting circuit and a function setting circuit are disposed between the input first stage and an address buffer. Each function setting mode buffer latches an internal address signal when a signal/RAS falls. Further, a function signal generating circuit is initialized by a power-on reset signal when a power supply is turned on.

摘要翻译： 输入第一级用于输入地址和地址键。 测试模式设置电路和功能设置电路设置在输入第一级和地址缓冲器之间。 当信号/ RAS下降时，每个功能设置模式缓冲器锁存一个内部地址信号。 此外，当电源接通时，功能信号发生电路由上电复位信号初始化。

公开(公告)号：US6061808A

公开(公告)日：2000-05-09

申请号：US332364

申请日：1999-06-14

申请人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

发明人： Tadaaki Yamauchi ,  Mikio Asakura ,  Takashi Ito

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/34 ,  G01R31/28 ,  G06F11/00

CPC分类号： G11C29/34

摘要： In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.

摘要翻译： 在预定的多位测试模式中，多位测试电路114将确定结果数据对RDM0和/ RDM0发送到RDM3和/ RDM3，每个RDM3和/ RDM3对应于从由一列选择线选择的存储器单元读取的数据的逻辑的匹配/不匹配 相应的一个存储单元平面块。 在每个存储单元平面块中，由单个列选择行选择的存储单元列可以被替换为单元。 根据确定结果数据RDM0和/ RDM0至RDM3和/ RDM3来替换包含有缺陷存储单元的存储单元列的单位。

公开(公告)号：US6064557A

公开(公告)日：2000-05-16

申请号：US333652

申请日：1999-06-16

申请人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

发明人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L23/50 ,  H01L27/02 ,  H01L27/108 ,  H02H3/22

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/49 ,  H01L27/0218 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/3011

摘要： A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

摘要翻译： 半导体器件包括形成在半导体衬底的表面处的MOS晶体管作为电容元件。 在衬底之上的第一电源互连，向晶体管的源极和漏极施加第一电源电位。 在第一互连之上的第二电源互连将第二电位施加到晶体管的栅极。 第三电源互连形成在与第二电源互连并联并连接到第二电源互连的上方。 外部源电位被下变频以适当地应用于第一，第二和第三电源互连。 该配置实现了对电源噪声不太敏感的半导体器件。

公开(公告)号：US5716889A

公开(公告)日：1998-02-10

申请号：US759199

申请日：1996-12-04

申请人： Takaharu Tsuji ,  Mikio Asakura ,  Kyoji Yamasaki

发明人： Takaharu Tsuji ,  Mikio Asakura ,  Kyoji Yamasaki

IPC分类号： G03F9/00 ,  H01L21/027 ,  H01L23/544 ,  H01L21/76

CPC分类号： G03F9/70 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/946 ,  Y10S438/975

摘要： A shot region includes a device region for forming a semiconductor device therein and a dicing region used for dicing. A portion of the peripheral edge portion of the shot region is defined by a portion of the peripheral edge portion of the device region. An alignment mark is arranged within the device region, and additional alignment marks are arranged within the dicing region. Thus, the number of the devices manufactured per wafer can be increased without degrading precision of alignment.

公开(公告)号：US5973554A

公开(公告)日：1999-10-26

申请号：US055779

申请日：1998-04-07

申请人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

发明人： Kyoji Yamasaki ,  Mikio Asakura ,  Tadaaki Yamauchi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L23/50 ,  H01L27/02 ,  H01L27/108 ,  H01L25/00

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/49 ,  H01L27/0218 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/3011

摘要： A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

公开(公告)号：US5875145A

公开(公告)日：1999-02-23

申请号：US795529

申请日：1997-02-05

申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C1/34

CPC分类号： G11C5/147

摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

摘要翻译： 半导体存储器件包括存储单元阵列，包括用于连接字线的列解码器和用于外围设备的VDC电路的外围电路，用于基于外部电源电压产生内部电源电压。 用于外设的VDC电路将内部电源电压提供给除了读出放大器，输出缓冲器和内部初始级之外的列解码器的外围电路。 响应于当列解码器被激活时从时钟发生电路输出的VDCE信号，外围设备的VDC电路的供应能力增加。 因此，即使当列解码器被激活时外围电路的功率消耗增加，也可以向外围电路提供足够的电力。