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    Synchronous memory with pipelined write operation
    1.
    发明授权
    Synchronous memory with pipelined write operation 失效
    具有流水线写入操作的同步存储器

    公开(公告)号：US5761150A

    公开(公告)日：1998-06-02

    申请号：US651873

    申请日：1996-05-21

    申请人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/413 ,  G06F12/00 ,  G11C7/10 ,  G11C8/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/06 ,  G11C11/418 ,  G11C7/1072 ,  G11C2207/2218

    摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

    摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

    Memory circuit improved in electrical characteristics
    3.
    发明授权
    Memory circuit improved in electrical characteristics 失效
    存储器电路改善了电气特性

    公开(公告)号：US5742551A

    公开(公告)日：1998-04-21

    申请号：US463851

    申请日：1995-06-05

    申请人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    发明人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    IPC分类号： H03F3/72 ,  H03K17/62 ,  G11C7/02

    CPC分类号： H03F3/72 ,  H03K17/6264 ,  H03F2203/7203

    摘要： A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.

    摘要翻译： 恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。 在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。 当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。 对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。 还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接， 提高存储电路的性能特点。 此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。

    Multiplex circuit arrangement for use with a semiconductor integrated circuit
    5.
    发明授权
    Multiplex circuit arrangement for use with a semiconductor integrated circuit 失效
    用于半导体集成电路的多路电路装置

    公开(公告)号：US5523713A

    公开(公告)日：1996-06-04

    申请号：US464344

    申请日：1995-06-05

    申请人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    发明人： Seigoh Yukutake ,  Yutaka Kobayashi ,  Takashi Akioka ,  Masahiro Iwamura

    IPC分类号： H03F3/72 ,  H03K17/62

    CPC分类号： H03F3/72 ,  H03K17/6264 ,  H03F2203/7203

    摘要： A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof. The bipolar transistors corresponding to the non-selection input signals are maintained OFF, through activating the current drawing circuits associated therewith, irrespective of the potential levels of the incoming input signals supplied to the base terminals thereof. In the emitter follower type multiplex circuit, a constant current source is also provided between the commonly connected emitters of the bipolar transistors and the power source of low potential. The multiplex arrangement effected can be of the collector dot type multiplex circuit. Such multiplex circuits are used with a semiconductor integrated circuit such as a memory circuit.

    摘要翻译： 公开了一种多路复用电路，其中组合了多个双极晶体管，并且将其各自的基极端子用作输入，从而构成射极跟随器型多路复用电路。 在这种射极跟踪器型多路复用电路中，通过在每个基极之间设置MOS晶体管和通过电阻器的电源的高电位之间来控制各个双极型晶体管的基极电位来实现非选择/选择的多路复用功能， 电流绘制电路。 根据这种方案，当进行一个输入信号的选择时，与其相对应的双极晶体管被允许基于提供给其基极的输入信号而导通。 与非选择输入信号相对应的双极晶体管通过激活与其相关的电流绘制电路而保持关闭，而不管提供给其基极的输入信号的电位电平如何。 在射极跟踪器型多路复用电路中，在双极晶体管的共同连接的发射极和低电位的电源之间也设置恒流源。 所实现的复用布置可以是集电极点型多路复用电路。 这种多路复用电路与诸如存储电路的半导体集成电路一起使用。

    Semiconductor memory with multiple sets & redundant cells
    6.
    发明授权
    Semiconductor memory with multiple sets & redundant cells 失效

    公开(公告)号：US5392246A

    公开(公告)日：1995-02-21

    申请号：US205161

    申请日：1994-03-03

    申请人： Noboru Akiyama ,  Kinya Mitsumoto ,  Takashi Akioka ,  Seigoh Yukutake

    发明人： Noboru Akiyama ,  Kinya Mitsumoto ,  Takashi Akioka ,  Seigoh Yukutake

    IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11L7/00

    CPC分类号： G11C29/804 ,  G11C29/24 ,  G11C29/808

    摘要： An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.

    Level shift circuit and power conversion unit
    7.
    发明授权
    Level shift circuit and power conversion unit 有权
    电平移位电路和电源转换单元

    公开(公告)号：US08299836B2

    公开(公告)日：2012-10-30

    申请号：US13029341

    申请日：2011-02-17

    申请人： Naoki Sakurai ,  Junichi Sakano ,  Seigoh Yukutake

    发明人： Naoki Sakurai ,  Junichi Sakano ,  Seigoh Yukutake

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0175

    摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.

    摘要翻译： 在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过 通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。 当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路 即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。

    LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT
    8.
    发明申请
    LEVEL SHIFT CIRCUIT AND POWER CONVERSION UNIT 有权
    电平转换电路和电源转换单元

    公开(公告)号：US20110227626A1

    公开(公告)日：2011-09-22

    申请号：US13029341

    申请日：2011-02-17

    申请人： Naoki SAKURAI ,  Junichi Sakano ,  Seigoh Yukutake

    发明人： Naoki SAKURAI ,  Junichi Sakano ,  Seigoh Yukutake

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0175

    摘要： In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.

    摘要翻译： 在电平移位电路中，当高电压侧的电源电压变化dV / dt发生并影响电路的逻辑电平时，在第一和第二逻辑电路中屏蔽并防止故障信号的通过 通过利用在设定侧和复位侧出现这种变化的事实，通过来自时间常数生成电路的信号或者预先发生电力电压变化的部分。 当在高电压侧产生电源电压变化dV / dt时，在该掩蔽的定时中的充分允许阻止了错误的信号被发送到触发器，并且控制信号从低电压侧电路 即使在半导体工艺中的每个元件存在生产变化时，也不会对高压侧电路产生故障。