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公开(公告)号：US5638335A
公开(公告)日：1997-06-10
申请号：US649166
申请日：1996-05-17
申请人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
发明人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
CPC分类号： G11C5/06 , G11C7/062 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.
摘要翻译： 一种存储器件，包括具有多个位的存储器阵列，包括奇偶校验位，并且包括多个存储器块，以及位结构改变部分，用于改变存储器阵列的输入/输出位，其中存储器块的数量 被规定为3的整数倍，并且多个存储块的输入/输出位是偶数。 因此，可以改变具有奇偶校验位并且能够将输入/输出位改变为多个位结构的半导体存储器的位结构，同时保持存储器块的位结构并且不增加传播延迟 时间。
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公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。
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公开(公告)号：US5392246A
公开(公告)日：1995-02-21
申请号：US205161
申请日：1994-03-03
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C29/24 , G11L7/00
CPC分类号： G11C29/804 , G11C29/24 , G11C29/808
摘要： An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.
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公开(公告)号：US5661693A
公开(公告)日：1997-08-26
申请号：US562194
申请日：1995-11-22
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C11/413 , G11C11/416 , G11C7/00
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1051
摘要： A synchronous memory device is provided in which the cycle time is shorter than conventional memory devices. For example, by providing an output latch in a sense amplifier on a bit line, the time period from input of a clock signal to latching data in the output latch is shortened. In case of plural bit lines, a selector for selecting data in a plural output latch and a latch for latching a sense amplifier selection are provided.
摘要翻译： 提供了一种同步存储器件，其中循环时间比常规存储器件短。 例如，通过在位线上的读出放大器中设置输出锁存器，从输入锁存器中的时钟信号输入到锁存数据的时间段被缩短。 在多位线的情况下，提供用于选择多个输出锁存器中的数据的选择器和用于锁存读出放大器选择的锁存器。
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5.发明授权Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。
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公开(公告)号：US5742551A
公开(公告)日：1998-04-21
申请号：US463851
申请日：1995-06-05
CPC分类号： H03F3/72 , H03K17/6264 , H03F2203/7203
摘要： A constant current source is connected in series to a current source circuit including a MOS transistor which is used as a current source for a differential output amplifier circuit, an emitter follower circuit or a source follower circuit used with a semiconductor integrated circuit. In a multiplex circuit, an input signal is inputted to each of base terminals of a plurality of bipolar transistors. When one input signal is selected, the bipolar transistor corresponding to the selected input signal is made to be operable with an input signal from a signal input terminal by a control circuit. The bipolar transistors corresponding to the non-selection input signals are turned OFF irrespective of potential levels of the individual input signals by current drawing circuits. There is also disclosed a semiconductor memory circuit having a plurality of memory cells, a memory cell selection scheme and a sense amplifier for amplifying data outputted from the selected memory cell, in which a constant current circuit is provided in series connection to the sense amplifier to enhance the performance characteristics of the memory circuit. Also, a plural memory array scheme is disclosed which employs multiplexing techniques connected to presense amplifier circuits of the respective memory arrays.
摘要翻译： 恒流源串联连接到电流源电路，该电流源电路包括用作差分输出放大器电路的电流源的MOS晶体管，射极跟随器电路或与半导体集成电路一起使用的源极跟随器电路。 在复用电路中，输入信号被输入到多个双极晶体管的每个基极端子。 当选择一个输入信号时，与所选择的输入信号相对应的双极晶体管可以通过控制电路与来自信号输入端的输入信号一起工作。 对应于非选择输入信号的双极晶体管截止，而与当前绘图电路的各个输入信号的电位电平无关。 还公开了具有多个存储单元的半导体存储器电路，存储单元选择方案和用于放大从所选择的存储单元输出的数据的读出放大器，其中恒定电流电路与读出放大器串联连接， 提高存储电路的性能特点。 此外，公开了一种多重存储器阵列方案，其采用连接到相应存储器阵列的预放大器电路的复用技术。
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7.发明授权
公开(公告)号：US5523713A
公开(公告)日：1996-06-04
申请号：US464344
申请日：1995-06-05
CPC分类号： H03F3/72 , H03K17/6264 , H03F2203/7203
摘要： A multiplex circuit is disclosed in which a plurality of bipolar transistors are combined and in which the respective base terminals thereof are used as inputs, thereby to construct an emitter follower type multiplex circuit. In such an emitter follower type multiplex circuit, the multiplexing function of non-selection/selection is effected by controlling the base potential of the respective bipolar transistors by providing a MOS transistor between each base and a high potential of the power source through a resistor and a current drawing circuit. In accordance with such a scheme, when a selection of one input signal is made, the bipolar transistor corresponding thereto is permitted to turn ON on the basis of an input signal supplied to the base terminal thereof. The bipolar transistors corresponding to the non-selection input signals are maintained OFF, through activating the current drawing circuits associated therewith, irrespective of the potential levels of the incoming input signals supplied to the base terminals thereof. In the emitter follower type multiplex circuit, a constant current source is also provided between the commonly connected emitters of the bipolar transistors and the power source of low potential. The multiplex arrangement effected can be of the collector dot type multiplex circuit. Such multiplex circuits are used with a semiconductor integrated circuit such as a memory circuit.
摘要翻译： 公开了一种多路复用电路，其中组合了多个双极晶体管，并且将其各自的基极端子用作输入，从而构成射极跟随器型多路复用电路。 在这种射极跟踪器型多路复用电路中，通过在每个基极之间设置MOS晶体管和通过电阻器的电源的高电位之间来控制各个双极型晶体管的基极电位来实现非选择/选择的多路复用功能， 电流绘制电路。 根据这种方案，当进行一个输入信号的选择时，与其相对应的双极晶体管被允许基于提供给其基极的输入信号而导通。 与非选择输入信号相对应的双极晶体管通过激活与其相关的电流绘制电路而保持关闭，而不管提供给其基极的输入信号的电位电平如何。 在射极跟踪器型多路复用电路中，在双极晶体管的共同连接的发射极和低电位的电源之间也设置恒流源。 所实现的复用布置可以是集电极点型多路复用电路。 这种多路复用电路与诸如存储电路的半导体集成电路一起使用。
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公开(公告)号：US07254068B2
公开(公告)日：2007-08-07
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。
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公开(公告)号：US20050128839A1
公开(公告)日：2005-06-16
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US06856559B2
公开(公告)日：2005-02-15
申请号：US10637549
申请日：2003-08-11
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。
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