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    Synchronous memory with pipelined write operation
    1.
    发明授权
    Synchronous memory with pipelined write operation 失效
    具有流水线写入操作的同步存储器

    公开(公告)号：US5761150A

    公开(公告)日：1998-06-02

    申请号：US651873

    申请日：1996-05-21

    申请人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/413 ,  G06F12/00 ,  G11C7/10 ,  G11C8/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/06 ,  G11C11/418 ,  G11C7/1072 ,  G11C2207/2218

    摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

    摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

    Semiconductor memory with multiple sets & redundant cells
    3.
    发明授权
    Semiconductor memory with multiple sets & redundant cells 失效

    公开(公告)号：US5392246A

    公开(公告)日：1995-02-21

    申请号：US205161

    申请日：1994-03-03

    申请人： Noboru Akiyama ,  Kinya Mitsumoto ,  Takashi Akioka ,  Seigoh Yukutake

    发明人： Noboru Akiyama ,  Kinya Mitsumoto ,  Takashi Akioka ,  Seigoh Yukutake

    IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11L7/00

    CPC分类号： G11C29/804 ,  G11C29/24 ,  G11C29/808

    摘要： An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.

    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels
    5.
    发明授权
    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
    用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作

    公开(公告)号：US5646897A

    公开(公告)日：1997-07-08

    申请号：US426384

    申请日：1995-04-21

    申请人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    发明人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    IPC分类号： G11C7/10 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C7/1051 ,  G11C11/41 ,  G11C2029/5004 ,  G11C29/34

    摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

    摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

    Semiconductor memory device and sense circuit
    6.
    发明授权
    Semiconductor memory device and sense circuit 失效
    半导体存储器件和感测电路

    公开(公告)号：US5734616A

    公开(公告)日：1998-03-31

    申请号：US694059

    申请日：1996-08-08

    申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

    摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

    Semiconductor memory device and information processor using the same
    7.
    发明授权
    Semiconductor memory device and information processor using the same 失效
    半导体存储器件和信息处理器使用它

    公开(公告)号：US6032229A

    公开(公告)日：2000-02-29

    申请号：US562187

    申请日：1995-11-22

    申请人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

    发明人： Takashi Hotta ,  Hideo Sawamoto ,  Noboru Akiyama ,  Takashi Akioka ,  Shigeya Tanaka

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G11C11/401 ,  G11C11/407 ,  G06F13/00

    CPC分类号： G06F12/0855

    摘要： An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

    摘要翻译： 通过提高处理器和半导体存储器件的吞吐量来提供整体上具有高性能的信息处理器。 信息处理器包括具有用于临时保存数据的缓冲器的存储器和具有存储器接口部分的处理器，该存储器接口部分用于在确定数据是否被写入存储器之前控制存储器将数据传送到缓冲器，并将数据写入所述存储器 记忆确定写作后。 通过调整阅读和写入之间的数据交换，对半导体器件的数据写入和读取进行流水线化。 由于可以同时执行从存储器的读取和写入的数据传送定时，因此可以通过流水线的处理来执行读取处理和写入处理，并且可以提高吞吐量。

    Semiconductor device, method of manufacturing the same and power-supply device using the same
    9.
    发明授权
    Semiconductor device, method of manufacturing the same and power-supply device using the same 失效
    半导体装置及其制造方法以及使用其的电源装置

    公开(公告)号：US08664716B2

    公开(公告)日：2014-03-04

    申请号：US12818485

    申请日：2010-06-18

    申请人： Takayuki Hashimoto ,  Takashi Hirao ,  Noboru Akiyama

    发明人： Takayuki Hashimoto ,  Takashi Hirao ,  Noboru Akiyama

    IPC分类号： H01L27/06

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/7803 ,  H02M3/1588 ,  Y02B70/1466

    摘要： In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n− type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n− type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n− type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.

    摘要翻译： 在横向型功率MOSFET中，通过抑制增加电池间距而实现高的击穿电压，并且降低反馈容量和导通电阻。 相对于n +型硅衬底的主表面垂直地设置具有高电阻的n型硅区域作为保持击穿电压的区域，并且具有高电阻的n型硅区域连接到 n +型硅衬底。 此外，导电物质通过绝缘物质填充在形成为从n +型硅衬底的主表面到达n +型硅衬底的沟槽内，以便与具有高电阻的n型硅区接触，并且 导电物质电连接到源电极。