公开(公告)号：US20130100750A1

公开(公告)日：2013-04-25

申请号：US13805287

申请日：2011-06-13

申请人： Takashi Ishiguro ,  Masayuki Sato ,  Tetsuo Hironaka ,  Masato Inagi ,  Hitoshi Shimazaki

发明人： Takashi Ishiguro ,  Masayuki Sato ,  Tetsuo Hironaka ,  Masato Inagi ,  Hitoshi Shimazaki

IPC分类号： G11C8/10 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C7/00 ,  H03K19/1776 ,  H03K19/17796

摘要： Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

公开(公告)号：US08952721B2

公开(公告)日：2015-02-10

申请号：US13805287

申请日：2011-06-13

申请人： Takashi Ishiguro ,  Masayuki Sato ,  Tetsuo Hironaka ,  Hitoshi Shimazaki

发明人： Takashi Ishiguro ,  Masayuki Sato ,  Tetsuo Hironaka ,  Hitoshi Shimazaki

IPC分类号： H03K19/173 ,  G11C8/10 ,  G11C7/00 ,  H03K19/177

CPC分类号： G11C8/10 ,  G11C7/00 ,  H03K19/1776 ,  H03K19/17796

摘要： Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

摘要翻译： 公开了旨在减少构成期望的逻辑电路的存储元件块的总数的半导体器件。 半导体器件包括N条地址线（N是等于2或更大的整数），N条数据线和多条存储部分。 每个存储部分包括地址解码器，用于对通过N个地址线提供的地址进行解码，以将字选择信号输出到字线; 以及连接到字线和数据线的多个存储元件，每个存储元件存储构成真值表的数据，并且经由数据线经由字线提供的字选择信号来输入或输出数据。 半导体器件适于使用于存储部分的N个地址线连接到其他N个存储部分的相应数据线，而用于存储部分的N个数据线连接到其他N的各个地址线 存储部分。

公开(公告)号：US08283945B2

公开(公告)日：2012-10-09

申请号：US13255846

申请日：2010-03-24

申请人： Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

发明人： Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K3/356

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

摘要： FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

摘要翻译： 作为常规可编程半导体器件的FPGA和MPLD具有差的成本性能，并未适当地考虑长信号线。 为了解决这个问题，在由多个MLUT组成的每个MLUT块中内置触发器，每个MLUT包括存储器和地址数据对。 相对于相邻MLUT之间的相邻线，引入了交替的相邻线，而在不相邻MLUT之间的互连的情况下，提供专用远距离线，此外，提供了环面互连网络。

公开(公告)号：US20120007635A1

公开(公告)日：2012-01-12

申请号：US13255846

申请日：2010-03-24

申请人： Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

发明人： Tetsuo Hironaka ,  Kazuya Tanigawa ,  Hiroaki Toguchi ,  Naoki Hirakawa ,  Takashi Ishiguro ,  Masayuki Sato

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/17792

摘要： FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.

摘要翻译： 作为常规可编程半导体器件的FPGA和MPLD具有差的成本性能，并未适当地考虑长信号线。 为了解决这个问题，在由多个MLUT组成的每个MLUT块中内置触发器，每个MLUT包括存储器和地址数据对。 相对于相邻MLUT之间的相邻线，引入了交替的相邻线，而在不相邻MLUT之间的互连的情况下，提供专用远距离线，此外，提供了环面互连网络。

公开(公告)号：US09347559B2

公开(公告)日：2016-05-24

申请号：US14129050

申请日：2012-06-21

申请人： Takuma Sekiya ,  Yuuichi Murayama ,  Masayuki Sato ,  Yuji Shima ,  Junya Takahashi ,  Masaki Moronuki

发明人： Takuma Sekiya ,  Yuuichi Murayama ,  Masayuki Sato ,  Yuji Shima ,  Junya Takahashi ,  Masaki Moronuki

IPC分类号： C23C14/06 ,  F16J9/26 ,  C23C14/32 ,  C23C28/04

CPC分类号： F16J9/26 ,  C23C14/0641 ,  C23C14/325 ,  C23C28/044 ,  C23C28/046

摘要： A high-thermal-conductivity piston ring having excellent scuffing resistance and wear resistance, which can be used in a high-heat-load environment in engines is provided. Also, to provide a piston ring with low friction for contributing to the improvement of fuel efficiency, a TiN coating as thick as 10-60 μm, in which the texture coefficient of a (111) plane is 1.2-1.65 in X-ray diffraction on the coating surface, with the texture coefficient of a (111) plane>the texture coefficient of a (220) plane>the texture coefficient of a (200) plane, is formed under the optimized ion plating conditions on a peripheral surface of the piston ring. Further, to obtain excellent sliding characteristics with low friction without losing excellent thermal conductivity of TiN, a hard amorphous carbon coating is formed on the TiN coating.

摘要翻译： 提供了可用于发动机的高热负荷环境中的具有优异的耐擦伤性和耐磨性的高导热性活塞环。 此外，为了提供具有低摩擦力的活塞环以有助于提高燃料效率，TiN涂层厚度为10-60μm，其中（111）面的织构系数在X射线衍射中为1.2-1.65 在涂层表面上，在优化的离子镀条件下，在（111）面的纹理系数>（220）面的织构系数>（200）面的织构系数上形成在 活塞环。 此外，为了在不损失TiN的优异导热性的情况下以低摩擦获得优异的滑动特性，在TiN涂层上形成硬的无定形碳涂层。

公开(公告)号：US20140137733A1

公开(公告)日：2014-05-22

申请号：US14129022

申请日：2012-06-21

申请人： Takuma Sekiya ,  Yuuichi Murayama ,  Masayuki Sato ,  Yuji Shima ,  Junya Takahashi ,  Masaki Moronuki

发明人： Takuma Sekiya ,  Yuuichi Murayama ,  Masayuki Sato ,  Yuji Shima ,  Junya Takahashi ,  Masaki Moronuki

IPC分类号： F02F5/00

CPC分类号： F02F5/00 ,  C23C14/0641 ,  C23C14/325 ,  C23C28/044 ,  C23C28/046 ,  F16J9/26

摘要： To provide a high-thermal-conductivity piston ring having excellent scuffing resistance and wear resistance, which can be used in a high-heat-load environment in engines, a TiN coating as thick as 10-60 μm, in which the texture coefficient of a (220) plane is 1.1-1.8 in X-ray diffraction on the coating surface, larger than those of (111) and (200) planes, is formed under the optimized ion plating conditions on a peripheral surface of the piston ring. Also, to obtain excellent sliding characteristics with low friction without losing excellent thermal conductivity of TiN, a hard amorphous carbon coating is formed on the TiN coating.

摘要翻译： 为了提供可用于发动机的高热负荷环境中的具有优异的抗划伤性和耐磨性的高导热性活塞环，厚度为10-60μm的TiN涂层，其中织构系数 在优选的离子镀条件下，在活塞环的周面上形成涂层表面的X射线衍射中的（220）面为1.1〜1.8，大于（111）面和（200）面的X射线衍射面。 另外，为了在不损失TiN的优异导热性的情况下以低摩擦力获得优异的滑动特性，在TiN涂层上形成硬质无定形碳涂层。

公开(公告)号：US08310812B2

公开(公告)日：2012-11-13

申请号：US12688954

申请日：2010-01-18

申请人： Masashige Ashizaki ,  Nario Niibo ,  Masayuki Sato ,  Yasuyuki Ito ,  Yukiyasu Sugihara

发明人： Masashige Ashizaki ,  Nario Niibo ,  Masayuki Sato ,  Yasuyuki Ito ,  Yukiyasu Sugihara

IPC分类号： H01G9/00 ,  H01G4/228 ,  H01G9/10 ,  H05K5/03

CPC分类号： H01G9/155 ,  H01G9/016 ,  H01G9/06 ,  H01G9/10 ,  H01G11/12 ,  H01G11/52 ,  H01G11/74 ,  H01G11/78 ,  H01G11/82 ,  H01G11/84 ,  Y02E60/13

摘要： An electric double layer capacitor has an element, a first terminal, a second terminal, a resin-made case, and a resin-made lid. A pair of electrodes are led out of the element. Each of the electrodes is connected to each of the first terminal and the second terminal. The element and an electrolyte are accommodated in the case having an opening top surface, and the lid is bonded to the top surface of the case. The joints of the first and second terminals are disposed at positions higher than the inner bottom of the case, and are exposed upward. The rims of the joints and intermediate conductive sections continuing from them are buried in the case, and the terminal sections continuing from the intermediate conductive sections are led from the side surface of the case to the outside.

摘要翻译： 双电层电容器具有元件，第一端子，第二端子，树脂制壳体和树脂制盖子。 一对电极从元件中引出。 每个电极连接到第一端子和第二端子中的每一个。 元件和电解质容纳在具有开口顶表面的壳体中，并且盖子结合到壳体的顶表面。 第一端子和第二端子的接头设置在比壳体的内底高的位置，并向上露出。 接合部的边缘和从它们继续的中间导电部分被掩埋在壳体中，并且从中间导电部分延伸的端子部分从壳体的侧表面引导到外部。

公开(公告)号：US20120274539A1

公开(公告)日：2012-11-01

申请号：US13394211

申请日：2011-11-22

申请人： Hirohiko Tashiro ,  Hiroshi Tanioka ,  Yoshitaka Oba ,  Masayuki Sato ,  Kenji Hara

发明人： Hirohiko Tashiro ,  Hiroshi Tanioka ,  Yoshitaka Oba ,  Masayuki Sato ,  Kenji Hara

IPC分类号： G09G5/00

CPC分类号： H04N1/00442 ,  G03G15/502 ,  G03G15/5087 ,  G03G2215/00109 ,  H04N2201/0094

摘要： It was necessary to prepare display data for the portrait and landscape display modes respectively, since the arrangement of the objects differs between the portrait and landscape display modes.

摘要翻译： 由于在纵向和横向显示模式之间的对象的布置不同，因此需要分别准备用于纵向和横向显示模式的显示数据。

公开(公告)号：US20110039008A1

公开(公告)日：2011-02-17

申请号：US12911118

申请日：2010-10-25

申请人： Kiyomi OONISHI ,  Yoshiyuki Hatano ,  Hirofumi Haruna ,  Yuka Kikuchi ,  Akira Sato ,  Hiroki Kannari ,  Masayuki Sato

发明人： Kiyomi OONISHI ,  Yoshiyuki Hatano ,  Hirofumi Haruna ,  Yuka Kikuchi ,  Akira Sato ,  Hiroki Kannari ,  Masayuki Sato

IPC分类号： A23C13/12 ,  A23D7/00 ,  A23C13/14

CPC分类号： C11C3/10 ,  A23D7/003 ,  A23D7/0053 ,  A23L9/20 ,  A23P20/12

摘要： A fat-and-oil composition comprising fats-and-oils A and B, and C and/or E, all being derived from vegetable fats-and-oils, the composition satisfying conditions (a), (b) and (c): A: at least one of lauric fats-and-oils, and fractionated, extremely hardened or transesterified oils of lauric fats-and-oils, B: a liquid oil, C: a transesterified oil of D derived from vegetable fats-and-oils, D: a fat-and-oil wherein the contents of saturated fatty acids and unsaturated fatty acids having 16 or more carbon atoms in all the constitutive fatty acids being 20%≦ but

摘要翻译： 包含脂肪和油的组合物A和B以及C和/或E全部来自植物油脂，所述组合物满足条件（a），（b）和（c） ：A：至少一种月桂酸脂肪油，以及分解，非常硬化或酯交换的月桂酸脂肪油，B：液体油，C：衍生自植物油脂的D的酯交换油， 油，D：脂肪和油，其中所有构成型脂肪酸中具有16个或更多个碳原子的饱和脂肪酸和不饱和脂肪酸的含量为20％＆amp; 但<75质量％，25％＆nlE; 但是分别为<70质量％，E为棕榈油和/或棕榈油的中熔分馏油，其中固体脂肪含量为50＆amp; 但在10℃下为<100％，20＆amp; 但在20℃下<90％，在35℃下<6％，所有来自植物油脂的脂肪和油成分中的A，B和C和/或E的含量 为（a）60质量％以上，98质量％，（b）1〜25质量％，（c）为1〜38质量％。

公开(公告)号：US20100252314A1

公开(公告)日：2010-10-07

申请号：US12746281

申请日：2008-12-16

申请人： Masashige Ashizaki ,  Masayuki Sato ,  Nario Niibo ,  Hiroaki Higashino

发明人： Masashige Ashizaki ,  Masayuki Sato ,  Nario Niibo ,  Hiroaki Higashino

IPC分类号： H05K1/16 ,  H01G9/00

CPC分类号： H01G9/016 ,  H01G9/08 ,  H01G9/155 ,  H01G11/74 ,  H01G11/82 ,  Y02E60/13

摘要： A coin-type electric double-layered capacitor of the present invention includes: a capacitor element; a lower cover for housing the capacitor element impregnated with an electrolyte; an upper cover for sealing an opening of the lower cover through an insulating ring-shaped packing; an upper terminal plate having one end portion connected to an outer surface of the upper cover; and a lower terminal plate having a first end portion connected to an outer surface of the lower cover and a second end portion provided with a through hole, the capacitor being configured such that at least part of the through hole is opened without being covered by an outer surface located on a bottom of the lower cover.

摘要翻译： 本发明的硬币型双层电容器包括：电容器元件; 用于容纳浸有电解质的电容器元件的下盖; 用于通过绝缘环形填料密封下盖的开口的上盖; 上端子板，其一端部连接到上盖的外表面; 以及下端子板，其具有连接到所述下盖的外表面的第一端部和设置有通孔的第二端部，所述电容器被构造成使得所述通孔的至少一部分被打开而不被覆盖 外表面位于下盖的底部。