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公开(公告)号：US5973359A
公开(公告)日：1999-10-26
申请号：US190929
申请日：1998-11-12
CPC分类号： H01L29/7395 , H01L27/0251 , H01L27/0255 , H01L29/1095 , H01L29/7808 , H01L29/7811
摘要： A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.CE of the series Zener diode array, such that the widths W.sub.1, W.sub.2 are held in respective ranges as represented by: W.sub.1 .gtoreq.0.15 V.sub.CE, and W.sub.2 .gtoreq.0.05 V.sub.CE. By controlling the widths W.sub.1, W.sub.2 to these ranges, respectively, the concentration of current into an end portion of the cell portion of the device can be prevented upon cut-off of current from an inductive load.
摘要翻译： 提供一种MOS型半导体器件，其包括用于过电压保护的串联齐纳二极管阵列，其设置在源极区域和具有与漏极电极基本相同的电位的电极之间，以及场致绝缘膜，串联齐纳二极管阵列 提供。 确定场绝缘膜的厚度T（μm）作为串联齐纳二极管阵列的钳位电压VCE（V）的函数，使得厚度T保持在如下所示的范围内：T> / = 2.0x10-3xVCE。 第二导电型隔离阱的与串联齐纳二极管阵列的场绝缘膜接近的部分的宽度W1（μm）和宽度W2（μm） 靠近不具有串联齐纳二极管阵列的场绝缘膜的第二导电型隔离阱被确定为串联齐纳二极管阵列的钳位电压VCE的函数，使得宽度W1，W2 保持在各自的范围内，如：W1> / = 0.15VCE，W2> / = 0.05VCE。 通过分别将宽度W1，W2控制到这些范围，可以在从感性负载切断电流时，防止电流进入器件的电池部分端部的电流的浓度。
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2.发明授权Circuit device for igniting internal combustion engine and semiconductor device for igniting internal combustion engine 失效用于点燃内燃机的电路装置和用于点燃内燃机的半导体装置
公开(公告)号：US5970964A
公开(公告)日：1999-10-26
申请号：US768360
申请日：1996-12-17
CPC分类号： F02P3/051 , F02P3/0552
摘要： A circuit is provided in which a voltage due to a minute current is applied to a gate terminal from a collector terminal when a collector voltage is higher than a gate voltage in an operation of current limitation. Thus, an increase in the collector voltage immediately after the operation of current limitation starts serves to boost the gate voltage. The boosted voltage suppress an abrupt increase in the collector voltage. When the collector voltage is reduced by oscillation, the action of boosting the gate voltage is lowered to suppress the reduction of the collector voltage.
摘要翻译： 提供一种电路，其中当电流限制的操作中集电极电压高于栅极电压时，由微小电流引起的电压从集电极端子施加到栅极端子。 因此，在电流限制开始运行之后立即增加集电极电压来提高栅极电压。 升压电压抑制集电极电压的突然增加。 当通过振荡减小集电极电压时，降低栅极电压升压的作用以抑制集电极电压的降低。
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公开(公告)号：US06462382B2
公开(公告)日：2002-10-08
申请号：US09811736
申请日：2001-03-19
IPC分类号： H01L2362
CPC分类号： H01L29/7395 , H01L25/071 , H01L27/0255 , H01L27/0635 , H01L29/1095 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.
摘要翻译： 提供一种MOS型半导体装置，其包括主MOS型半导体器件，连接在控制输入端子（G）和主MOS型半导体器件的控制输入端口（g）之间的内部控制电路以及连接的保护器件 控制输入端子（G）和设备的输出端子（S）之一，用于保护半导体器件或内部控制电路免受过电压。 保护装置包括：第一分支，包括由在半导体衬底上沉积在绝缘膜上的多晶硅层组成的齐纳二极管（Z1p）;以及包括形成在半导体衬底的表面层中的齐纳二极管（Z21）的第二支路， 以及二极管（Z3pr），其由沉积在半导体衬底上的绝缘膜上的多晶硅层构成，并且与齐纳二极管（Z21）反向连接。 第一和第二分支彼此并联连接。
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公开(公告)号：US06229180B1
公开(公告)日：2001-05-08
申请号：US09238855
申请日：1999-01-27
IPC分类号： H01L2362
CPC分类号： H01L29/7395 , H01L25/071 , H01L27/0255 , H01L27/0635 , H01L29/1095 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.
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公开(公告)号：US5621601A
公开(公告)日：1997-04-15
申请号：US314320
申请日：1994-09-28
申请人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
发明人： Tatsuhiko Fujihira , Shin Kiuchi , Kazuhiko Yoshida , Yukio Yano , Kazunori Oyabe , Shoichi Furuhata , Tetsuhiro Morimoto
CPC分类号： H03K17/0822 , H01L27/0248 , H03F1/52 , H03K17/0828
摘要： The disclosed invention is designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current. This is accomplished by separating the gates of the main transistor and the current detector transistor; by setting a shorter time constant for the gate circuit of the current detector transistor than that of the gate circuit of the main transistor; by feeding the detection signal obtained from the current detecting means which detects the current i of the current detector transistor proportional to the current I flowing through the main transistor, to the control means; and by controlling the gate potentials of both transistors to protect the main transistor from the over-current by feeding the comparison output Sd from the comparator circuit, which compares the voltage of the signal Vd with the reference voltage Vr, to the control circuit.
摘要翻译： 所公开的发明被设计为防止在绝缘栅极控制晶体管的过电流保护装置中经常发生的振荡。 该装置提高了电流检测中的响应，防止振荡，提高了防过电流的保护速度。 这通过分离主晶体管和电流检测器晶体管的栅极来实现; 通过为电流检测器晶体管的栅极电路设置比主晶体管的栅极电路的时间常数更短的时间常数; 通过将检测到与流过主晶体管的电流I成比例的电流检测器晶体管的电流i的电流检测装置获得的检测信号馈送到控制装置; 并且通过控制两个晶体管的栅极电位，通过将比较电路的比较输出Sd与信号Vd与参考电压Vr进行比较来控制主晶体管的过电流来保护主晶体管。
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公开(公告)号：US06911692B2
公开(公告)日：2005-06-28
申请号：US10646590
申请日：2003-08-22
IPC分类号： H01L23/29 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7802 , H01L23/293 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/4238 , H01L29/7395 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A MOS semiconductor device includes n−-type surface regions, which are extended portions of an n−-type drift layer 12 extended to the surface of the semiconductor chip. Each n−-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n−-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 μm or less.
摘要翻译： 一种MOS半导体器件包括n + O - 型表面区域，其是延伸到半导体芯片的表面的n + O - 型漂移层12的延伸部分。 每一个n型 - 表面区域14成形为由p型阱区域围绕的条纹。 包括n + +型区域15在内的n + - 型表面区域14和p型阱区域13之间的表面积比为0.01〜0.2。 MOS半导体器件在其击穿区域中进一步包括多个保护环，其数量等于或大于根据以下等式计算的数n：n =（击穿电压Vbr（V））/ 100 ，相邻保护环之间的间隔设定为1um以下。
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公开(公告)号：US5990518A
公开(公告)日：1999-11-23
申请号：US164487
申请日：1998-10-01
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/1095 , H01L29/7802 , H01L29/0696
摘要： An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.+ drain layer 2. A junction face 20 of p-type base region 3 and n.sup.- layer 1 has a finite radius of curvature such that the depth from the surface of p.sup.+ region 5 to junction face 20 is deepest beneath the center of p.sup.+ region 5.
摘要翻译： n +漏极层2上的n +漏极层2和n层1构成用于半导体装置的衬底。 p型基极区域3在n层1的表面部分中。在p型基极区域3的表面部分中形成n +源极区域6.比n +源极区域6更深的p +区域5 比p型基极区域3部分地重叠n +源极区域6，并且充分地延伸到由n +源极区域6包围的p型基极区域3的部分中。沟道部分7在p型基极区域3的表面部分中 在n层1和n +源极区域6之间延伸。栅极电极8设置在通道部分7之上，栅极绝缘膜9插入其间。 源极电极11与p +区域5和n +源极区域6接触。栅电极8上的层间绝缘膜10使源电极11与栅电极8绝缘。漏电极12在n +漏极层2的表面上。 p型基极区域3和n层1的接合面20具有有限的曲率半径，使得从p +区域5的表面到结面20的深度最深在p +区域5的中心下方。
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公开(公告)号：US5723890A
公开(公告)日：1998-03-03
申请号：US643760
申请日：1996-05-06
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/94
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/7395 , H01L29/7802 , H01L29/0847 , H01L29/402 , H01L29/4238
摘要： A MOS type semiconductor device with improved voltage and avalanche withstand capability includes a rectangular channel region of the second conductivity type formed in a surface layer of a semiconductor substrate of the first conductivity type, a heavily doped well region formed in the central part of the channel region, source regions of the first conductivity type formed in a surface layer of the channel region, and a surface MOS structure. The quadrangular cells are arranged so that a side of the cell may contact with a side of the neighboring cell. By joining the short sides of the neighboring channel regions, protruding portions such as the corners, to which the avalanche current tend to localize, of the channel region are eliminated. As a result, the avalanche withstand capability of the MOSFET is improved. Further, since the curvature of the depletion layer becomes small, the withstand voltage is improved.
摘要翻译： 具有改善的电压和雪崩耐受能力的MOS型半导体器件包括形成在第一导电类型的半导体衬底的表面层中的第二导电类型的矩形沟道区，形成在沟道的中心部分的重掺杂阱区 形成在沟道区的表面层中的第一导电类型的区域，源极区和表面MOS结构。 四边形单元被布置成使得单元的一侧可以与相邻单元的一侧接触。 通过连接相邻通道区域的短边，消除了沟道区域中雪崩电流倾向于定位的拐角等突出部分。 结果，提高了MOSFET的雪崩承受能力。 此外，由于耗尽层的曲率变小，耐电压提高。
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公开(公告)号：US06246092B1
公开(公告)日：2001-06-12
申请号：US09042544
申请日：1998-03-17
IPC分类号： H03K1728
CPC分类号： H01L29/7808 , H01L27/0248 , H01L27/0629 , H01L29/402 , H01L29/7811 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.
摘要翻译： 提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。 设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。 第二MOS型半导体器件的栅电极连接到公共漏电极。 半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。 每对齐纳二极管彼此反向连接。
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公开(公告)号：US5869372A
公开(公告)日：1999-02-09
申请号：US555426
申请日：1995-11-09
申请人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
发明人： Tatsuhiko Fujihira , Seiji Momota , Takeyoshi Nishimura , Kazutoshi Sugimura , Masao Yoshino , Takashi Kobayashi
IPC分类号： H01L21/28 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/316 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/266
摘要： A semiconductor device manufacturing process is disclosed in which one processing step is reduced by replacing the photoresist film conventionally used for masking in the formation of the heavily doped n-type layer by an oxide film, and by monitoring, in the monitor region, the simultaneous formation of the contact holes in the oxide films different in the respective thickness thereof. An n+ region is formed by using a second insulation film and a polysilicon gate electrode formed on a semi-conductor wafer as masks for implanting arsenic ions. Further, a contact hole to be formed on a p-type region covered with a fourth insulation film and a second insulation film and a contact hole to be formed on the n+ region covered with the fourth insulation film are formed simultaneously under the monitoring of the formation of the contact holes in a monitor region.
摘要翻译： 公开了一种半导体器件制造方法，其中通过用氧化膜替代常规用于形成重掺杂n型层的掩模的光致抗蚀剂膜，并且通过在监测区域中监测同时 形成不同厚度的氧化膜中的接触孔。 通过使用形成在半导体晶片上的第二绝缘膜和多晶硅栅极作为用于注入砷离子的掩模来形成n +区。 此外，在被覆有第四绝缘膜的p型区域上形成的接触孔和被覆有第四绝缘膜的n +区域上形成的第二绝缘膜和接触孔同时形成在 在监视器区域中形成接触孔。
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