公开(公告)号：US06838313B2

公开(公告)日：2005-01-04

申请号：US10616827

申请日：2003-07-10

申请人： Takashi Kumamoto ,  Kinya Ichikawa

发明人： Takashi Kumamoto ,  Kinya Ichikawa

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/44

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for producing a molded flip chip package is described. According to one embodiment, an incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold, and a resin is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate, and the resin is cured by maintaining the mold at an elevated temperature for a predetermined amount of time.

摘要翻译： 描述了用于制造模制倒装芯片封装的方法。 根据一个实施例，将包括薄基板和硅芯片的不完整的倒装芯片封装放置在模具中，并且将树脂注入填充倒装芯片的表面与相邻基板之间的间隙的模具中，并且树脂 通过将模具保持在高温下预定的时间量来固化。

公开(公告)号：US06632704B2

公开(公告)日：2003-10-14

申请号：US09741535

申请日：2000-12-19

申请人： Takashi Kumamoto ,  Kinya Ichikawa

发明人： Takashi Kumamoto ,  Kinya Ichikawa

IPC分类号： H01L2144

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L21/563 ,  H01L21/565 ,  H01L24/28 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, preferably epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

摘要翻译： 描述了用于制造模制倒装芯片封装的方法。 将包括薄基板和硅芯片的不完全倒装芯片封装放置在模具中。 将树脂（优选环氧树脂）注入填充倒装芯片的表面与相邻基底之间的间隙的模具中。 此外，形成加强结构以提高薄衬底的整体刚度和整体的包装。

公开(公告)号：US07132311B2

公开(公告)日：2006-11-07

申请号：US10206007

申请日：2002-07-26

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US07132739B2

公开(公告)日：2006-11-07

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L23/31

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US20050085034A1

公开(公告)日：2005-04-21

申请号：US10975839

申请日：2004-10-28

申请人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

发明人： Masayuki Akiba ,  Kinya Ichikawa ,  Jiro Kubota ,  Takashi Kumamoto

IPC分类号： H01L21/56 ,  H01L21/8238 ,  H01L21/98 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065 ,  H01L29/74

CPC分类号： H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06593

摘要： Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

摘要翻译： 描述了用于封装半导体管芯堆叠的系统和方法。 可以形成半导体管芯堆叠，例如通过将管芯连接到附接到框架上的柔性印刷电路支架并堆叠支撑件，然后通过使液体密封剂流过骰子堆叠并固化液体密封剂来进行封装。 管芯支撑件可以包含允许液体密封剂围绕骰子堆流动的密封剂流动开口，例如矩形狭缝。

公开(公告)号：US20140335686A1

公开(公告)日：2014-11-13

申请号：US13891279

申请日：2013-05-10

申请人： Xavier F. Brun ,  Takashi Kumamoto ,  Sufi Ahmed

发明人： Xavier F. Brun ,  Takashi Kumamoto ,  Sufi Ahmed

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/11442 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/12042 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00

摘要： A tape capable of laser ablation may be used in the formation of microelectronic interconnects, wherein the tape may be attached to bond pads on a microelectronic device and vias may be formed by laser ablation through the tape to expose at least a portion of corresponding bond pads. The microelectronic interconnects may be formed on the bond pads within the vias, such as by solder paste printing and solder reflow. The laser ablation tape can be removed after the formation of the microelectronic interconnects.

摘要翻译： 可以使用能够进行激光烧蚀的胶带来形成微电子互连，其中胶带可以附着到微电子器件上的接合焊盘，并且通孔可以通过激光烧蚀形成，以通过带暴露至少一部分相应的焊盘 。 微电子互连可以形成在通孔内的接合焊盘上，例如通过焊膏印刷和焊料回流。 在形成微电子互连后，可以去除激光烧蚀带。

公开(公告)号：US07145226B2

公开(公告)日：2006-12-05

申请号：US10610854

申请日：2003-06-30

申请人： Takashi Kumamoto

发明人： Takashi Kumamoto

IPC分类号： H01L23/02 ,  H01L25/065 ,  H05K1/14 ,  H05K25/065 ,  H05K3/34

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/3511 ,  H01L2924/00

摘要： This invention relates to an apparatus and methods for increasing the microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.

摘要翻译： 本发明涉及一种用于通过堆叠阵列中的多个微电子封装并且控制封装以封装可扩展性而不施加载体衬底并且不限制信号和输入/输出引线的数量来增加微电子封装密度的装置和方法。 具体地说，其中具有导电立管的中间基板用于使得封装的间距控制能够封装互连，控制间隔距离并充当微电子封装加强件。

公开(公告)号：US20050006767A1

公开(公告)日：2005-01-13

申请号：US10910933

申请日：2004-08-03

申请人： Takashi Kumamoto

发明人： Takashi Kumamoto

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/563 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00

摘要： Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.

摘要翻译： 用于凸起的晶片和模具的多用途平面化/后研磨/预填充布置，其中平面化涂层在后研磨和随后的安装操作中提供对晶片或模具的电路表面的改进的和持续的表面保护， 并且在后研磨和随后的安装操作中提供了晶片和模具的改进的加强/加强。

公开(公告)号：US07138709B2

公开(公告)日：2006-11-21

申请号：US10663485

申请日：2003-09-15

申请人： Takashi Kumamoto

发明人： Takashi Kumamoto

IPC分类号： H01L23/02

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/3511 ,  H01L2924/00

摘要： This invention relates to an apparatus and method for increasing microelectronic package density by stacking multiple microelectronic packages in an array and controlling package to package scalability without stressing the carrier substrates and without limiting the number of signal and input/output leads. Specifically, an intermediate substrate having conductive risers therein is used to enable pitch control of the package to package interconnection, control of the standoff distance and act as a microelectronic package stiffener.

摘要翻译： 本发明涉及一种用于通过将阵列中的多个微电子封装堆叠并且控制封装以封装可扩展性而不施加载体衬底而不限制信号和输入/输出引线的数量来增加微电子封装密度的装置和方法。 具体地说，其中具有导电立管的中间基板用于使得封装的间距控制能够封装互连，控制间隔距离并充当微电子封装加强件。

公开(公告)号：US07071572B2

公开(公告)日：2006-07-04

申请号：US10910933

申请日：2004-08-03

申请人： Takashi Kumamoto

发明人： Takashi Kumamoto

IPC分类号： H01L23/48 ,  H01L21/48

CPC分类号： H01L21/6835 ,  H01L21/563 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00

摘要： Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.

摘要翻译： 用于凸起的晶片和模具的多用途平面化/后研磨/预填充布置，其中平面化涂层在后研磨和随后的安装操作中提供对晶片或模具的电路表面的改进的和持续的表面保护， 并且在后研磨和随后的安装操作中提供了晶片和模具的改进的加强/加强。