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公开(公告)号：US20120217813A1
公开(公告)日：2012-08-30
申请号：US13323464
申请日：2011-12-12
申请人： Takashi Takeuchi , Takahide Terada , Kenichi Osada
发明人： Takashi Takeuchi , Takahide Terada , Kenichi Osada
IPC分类号： H02J1/00
CPC分类号： H01M10/4207 , G01R31/396 , H01M6/42 , H01M10/482 , Y10T307/685
摘要： A storage battery system in which multiple storage battery modules are connected in series and such that deteriorated storage battery modules may be made replaceable without causing dielectric breakdown. The storage battery system is one that has multiple storage battery modules connected in series and has a mechanism of, when the storage battery module is detached, disconnecting power source line connected to the storage battery modules after disconnecting communication line connected to the storage battery modules.
摘要翻译： 一种蓄电池系统，其中多个蓄电池模块串联连接，并且使劣化的蓄电池模块可以被替换而不引起电介质击穿。 蓄电池系统是具有串联连接的多个蓄电池模块的蓄电池模块，具有在断开连接到蓄电池模块的通信线路之后断开与蓄电池模块连接的电源线的机构。
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2.发明授权Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层公开(公告)号：US09286968B2
公开(公告)日：2016-03-15
申请号：US13616435
申请日：2012-09-14
IPC分类号： H01L29/76 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致微图案化困难。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。
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公开(公告)号：US08633684B2
公开(公告)日：2014-01-21
申请号：US12917523
申请日：2010-11-02
IPC分类号： G01R5/14
CPC分类号： G06F1/3203 , G06F1/206 , H01L21/67276 , Y02D10/16
摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.
摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。
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公开(公告)号：US08531872B2
公开(公告)日：2013-09-10
申请号：US13350340
申请日：2012-01-13
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.
摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。
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公开(公告)号：US08451050B2
公开(公告)日：2013-05-28
申请号：US12987112
申请日：2011-01-08
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , H03K19/0016
摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.
摘要翻译： 信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管 电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为 改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。
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公开(公告)号：US08270230B2
公开(公告)日：2012-09-18
申请号：US13353949
申请日：2012-01-19
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
CPC分类号： G11C8/08 , G11C11/412
摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。
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公开(公告)号：US08264870B2
公开(公告)日：2012-09-11
申请号：US12891208
申请日：2010-09-27
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。
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公开(公告)号：US20120217620A1
公开(公告)日：2012-08-30
申请号：US13461848
申请日：2012-05-02
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , G11C5/02 , H01L25/18 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05599
摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。
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公开(公告)号：US08253227B2
公开(公告)日：2012-08-28
申请号：US12606812
申请日：2009-10-27
申请人： Kenichi Osada , Makoto Saen , Futoshi Furuta
发明人： Kenichi Osada , Makoto Saen , Futoshi Furuta
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/50 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/15311 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.
摘要翻译： 提供能够实现I / O处理性能提高，功耗降低，成本降低的半导体集成电路装置。 提供了一种半导体集成电路器件，其包括例如堆叠并安装的多个半导体芯片，具有通过通孔总线连接的数据收发终端的芯片和数据发送和接收通过总线使用最低的源 芯片的内部核心电路的电源电压之间的电压。 根据此，通过贯通孔将第n芯片的源极电压端子与源极电压端子连接，用于其他半导体芯片的数据收发电路。
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公开(公告)号：US20120136596A1
公开(公告)日：2012-05-31
申请号：US13388990
申请日：2009-09-14
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
CPC分类号： H01L22/30 , H01L23/50 , H01L23/5286 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to sufficiently supply power to three-dimensionally stacked LSI chips and to dispose common through vias in chips of different types. Also, another object is to propose a new test method for power-supply through silicon vias. In order to achieve these objects, a semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction; a plurality of signal-line through vias that are connected to the first semiconductor substrate and transmit signals, which are output from the first circuit block, to a second circuit block formed on another second semiconductor substrate; and a plurality of power-supply through vias for supplying power to the first circuit block, and in the semiconductor device, the plurality of power-supply through vias are formed at edges of the first semiconductor substrate along the third and fourth sides and are formed in a plurality of rows in the first direction. Also, each of the circuit blocks has a power consuming mode in which power larger than the power consumption in a normal mode is consumed.
摘要翻译： 本发明的目的是为三维堆叠的LSI芯片充分供电，并在通常的通孔中配置不同类型的芯片。 此外，另一个目的是提出一种通过硅通孔供电的新测试方法。 为了实现这些目的，半导体器件包括：第一电路块，形成在第一半导体衬底上，第一半导体衬底具有沿第一方向延伸的第一和第二侧面，以及沿与第一方向相交的第二方向延伸的第三和第四侧面; 连接到第一半导体衬底并将从第一电路块输出的发射信号的多个信号线通孔传送到形成在另一第二半导体衬底上的第二电路块; 以及多个用于向第一电路块提供电力的通孔的供电通道，并且在半导体器件中，多个电源通孔沿着第三和第四侧形成在第一半导体衬底的边缘处，并且形成 在第一方向上的多行中。 此外，每个电路块具有消耗大于正常模式下的功率消耗的功率的功耗模式。
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