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1.发明授权Differential input interface circuit and method for adjusting DC levels of differential input signals 失效差分输入接口电路和调整差分输入信号直流电平的方法公开(公告)号：US06259300B1
公开(公告)日：2001-07-10
申请号：US09477143
申请日：2000-01-03
申请人： Takeo Yasuda , Naohisa Hatani
发明人： Takeo Yasuda , Naohisa Hatani
IPC分类号： H03L500
CPC分类号： H03M1/1295 , H03F3/45475 , H03F3/45941 , H03M1/0682
摘要： A differential input interface circuit includes a reference level generation stage generating a DC level that coincides with the DC level within the system; capacitors for cutting-off the DC level of the differential input signals; resistors for matching the average of the non-inverting phase signal and the inverting phase signal of the differential input signals from which the DC levels have been cut-off on the output DC level generated by the reference level generation stage. Thus, a differential input interface circuit make it possible to match the DC level of differential inputs to the DC level within a system which is responsive to the differential inputs.
摘要翻译： 差分输入接口电路包括产生与系统内的DC电平一致的DC电平的参考电平产生级; 用于切断差分输入信号的直流电平的电容器; 用于匹配由参考电平产生级产生的输出DC电平上的DC电平已被截止的差分输入信号的非反相相位信号和反相相位信号的平均值的电阻器。 因此，差分输入接口电路使得可以将差分输入的DC电平与响应于差分输入的系统内的DC电平相匹配。
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2.发明申请Phase adjustment device, phase adjustment method, and semiconductor integrated circuit 审中-公开相位调整装置，相位调整方法和半导体集成电路公开(公告)号：US20060232314A1
公开(公告)日：2006-10-19
申请号：US11396453
申请日：2006-04-04
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00058 , H03L7/07 , H03L7/0814
摘要： A phase adjustment device which adjusts a phase difference between a first output pulse signal and a second output pulse signal according to a phase difference between a first input pulse signal and a second input pulse signal, the phase adjustment device including: a first selection unit which selects one of the first input pulse signal and an adjustment pulse signal that is used for adjustment; a second selection unit which selects one of the second input pulse signal and the adjustment pulse signal; a first delay unit which delays the signal selected by the second selection unit, and a delay amount of the first delay unit is adjustable; a first output unit which outputs, as the first output pulse signal, the signal selected by the first selection unit; a second output unit which outputs, as the second output pulse signal, the signal delayed by the first delay unit; and a phase adjustment unit which adjusts the delay amount so as to equalize phases of the first output pulse signal and the second output pulse signal, in the case where both the first selection unit and the second selection unit have selected the adjustment pulse signal.
摘要翻译： 一种相位调整装置，其根据第一输入脉冲信号和第二输入脉冲信号之间的相位差来调整第一输出脉冲信号和第二输出脉冲信号之间的相位差，所述相位调整装置包括：第一选择单元， 选择第一输入脉冲信号和用于调整的调整脉冲信号之一; 第二选择单元，其选择第二输入脉冲信号和调整脉冲信号中的一个; 第一延迟单元，其延迟由第二选择单元选择的信号，并且第一延迟单元的延迟量是可调节的; 第一输出单元，其输出由第一选择单元选择的信号作为第一输出脉冲信号; 输出由第一延迟单元延迟的信号作为第二输出脉冲信号的第二输出单元; 以及在所述第一选择单元和所述第二选择单元都选择了所述调整脉冲信号的情况下，调整所述延迟量以均衡所述第一输出脉冲信号和所述第二输出脉冲信号的相位的相位调整单元。
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公开(公告)号：US20070008282A1
公开(公告)日：2007-01-11
申请号：US11479011
申请日：2006-06-30
IPC分类号： G09G5/08
摘要： A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k−1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.
摘要翻译： 本发明的流水线A / D转换器包括多个用于A / D转换的工作级和基于从每个级输出的数字信号输出A / D转换的信号的数字计算部分。 在每个阶段中，来自前一级的模拟信号在第一周期中被无源元件C 1和C 2采样，并且在第二周期中将无源元件中的一个作为反馈元件用于执行与/ 相对于被另一无源元件采样的信号。 通过数字计算部分的控制，使用测试信号Tink而不是模拟输出信号Vo（k-1），并且基于通过每个操作获得的数字信号来检测和校正唯一的转换误差值 的阶段。 可以获得可以抑制由模拟信号处理所使用的电容器的相对误差引起的转换误差而不降低A / D转换速度的高分辨率A / D转换。
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公开(公告)号：US06683335B2
公开(公告)日：2004-01-27
申请号：US09887821
申请日：2001-06-22
申请人： Naohisa Hatani , Manabu Ohkubo
发明人： Naohisa Hatani , Manabu Ohkubo
IPC分类号： H01L2710
CPC分类号： H01L27/11803
摘要： In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.
摘要翻译： 在具有沿着第一轴的PFET和NFET的相邻线的栅极阵列中，PFET和/或NFET的一些栅极延伸到阱之间并且沿着晶体管的第一（x）轴沿着轴重叠的区域，因此 第n晶体管的扩展栅极，（n-1）非延迟晶体管的栅极和相反极性的第（n-1）非延迟晶体管的栅极沿着垂直于（y）的轴线（y） 到第一轴。 在矩形布局中，右上方晶体管（具有扩展栅极）通过沿着y轴的短连接连接到左下方晶体管。
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公开(公告)号：US06337646B1
公开(公告)日：2002-01-08
申请号：US09422635
申请日：1999-10-21
申请人： Naohisa Hatani , Manabu Ohkubo
发明人： Naohisa Hatani , Manabu Ohkubo
IPC分类号： H03M106
CPC分类号： H03M1/0612 , H03M1/785
摘要： To provide a D/A converter and a D/A converting method in which a nonlinear error of an analog output obtained in accordance with a digital input can be decreased without using any specific analog process. An n-bit D/A converter (2) includes: correction signal generating means (4) for generating an m-bit digital correction signal (wherein m is a positive integer) in accordance with an n-bit digital input signal D (wherein n is a positive integer of 2 or more); and D/A conversion means (6) for converting an (n+m)-bit digital signal consisting of the n-bit input signal D and the m-bit correction signal into an analog signal.
摘要翻译： 提供D / A转换器和D / A转换方法，其中可以在不使用任何特定的模拟处理的情况下减少根据数字输入获得的模拟输出的非线性误差。一个n位D / A转换器（2 ）包括：根据n位数字输入信号D（其中n是2或更大的正整数）产生m位数字校正信号（其中m是正整数）的校正信号发生装置（4） ; 以及用于将由n位输入信号D和m位校正信号组成的（n + m）位数字信号转换为模拟信号的D / A转换装置（6）。
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公开(公告)号：US20100246607A1
公开(公告)日：2010-09-30
申请号：US12750232
申请日：2010-03-30
IPC分类号： H04J3/00
CPC分类号： H04J3/047 , H04L7/0008
摘要： Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.
摘要翻译： n个信号转换检测部中的每一个检测与信号转变检测部对应的第一输入信号或第二输入信号中的至少一个的信号电平的转变。 当由n个信号转换检测部分中的至少一个检测到信号转换时，时分控制部分根据系统时钟输出控制脉冲。 n个输出切换部分中的每一个根据控制脉冲输出与输出切换部分相对应的第一或第二输入信号作为多路复用信号。
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公开(公告)号：US07652690B2
公开(公告)日：2010-01-26
申请号：US11723117
申请日：2007-03-16
申请人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
发明人： Naohisa Hatani , Mitsuhiko Otani , Kouji Yamaguchi
IPC分类号： H04N5/228
CPC分类号： H04N5/361 , H04N5/3575 , H04N5/3655
摘要： A front-end signal processing circuit that stabilizes a black level of an output signal of an image sensor in a prescribed set level, without being influenced by a DC offset component of circuit elements making up a feedback loop, and an imaging device including such the front-end signal processing circuit, are provided.The front-end signal processing circuit includes a feedback loop made up of a luminance detecting/digitizing section and a black level clamp section, and clamps a black level of an output signal of an image sensor to a prescribed set level. The front-end signal processing circuit further includes an offset correction section. The offset correction section stores an offset value being a difference between a signal level of an OB region of the image sensor and the prescribed level, subtracts the offset value from a digital luminance signal corresponding to an effective pixel region of the image sensor, and outputs the obtained signal.
摘要翻译： 一种前端信号处理电路，其在规定的设定电平下稳定图像传感器的输出信号的黑电平，而不受构成反馈回路的电路元件的DC偏移分量的影响;以及成像装置， 前端信号处理电路。 前端信号处理电路包括由亮度检测/数字化部分和黑电平钳位部分构成的反馈回路，并将图像传感器的输出信号的黑电平钳位到规定的设定电平。 前端信号处理电路还包括偏移校正部分。 偏移校正部存储作为图像传感器的OB区域的信号电平与规定电平之间的差的偏移值，从与图像传感器的有效像素区域对应的数字亮度信号中减去偏移值，并输出 获得的信号。
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公开(公告)号：US20090154268A1
公开(公告)日：2009-06-18
申请号：US12332844
申请日：2008-12-11
CPC分类号： G11C7/22 , G11C7/222 , H03D13/004 , H03L7/0812 , H03L7/0891
摘要： A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.
摘要翻译： 可变延迟电路连续地延迟输入时钟以产生具有不同相位的多个延迟时钟。 相位比较电路接收作为延迟时钟或输入时钟之一的第一参考时钟和作为延迟时钟之一并且其相位滞后于第一参考时钟之一的第二参考时钟，指定一个 并且根据第一参考时钟和第二参考时钟的电压电平仅在验证间隔期间比较第一和第二参考时钟的相位。 延迟控制电路根据由相位比较电路获得的比较结果控制可变延迟电路中的延迟时间。
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公开(公告)号：US08325647B2
公开(公告)日：2012-12-04
申请号：US12750232
申请日：2010-03-30
CPC分类号： H04J3/047 , H04L7/0008
摘要： Each of n signal transition detection sections detects a transition of the signal level of at least one of a first input signal or a second input signal corresponding to the signal transition detection section. A time-division control section outputs a control pulse according to a system clock when a signal transition is detected by at least one of the n signal transition detection sections. Each of n output switching sections outputs either the first or the second input signal corresponding to the output switching section as a multiplexed signal according to the control pulse.
摘要翻译： n个信号转换检测部中的每一个检测与信号转变检测部对应的第一输入信号或第二输入信号中的至少一个的信号电平的转变。 当由n个信号转换检测部分中的至少一个检测到信号转换时，时分控制部分根据系统时钟输出控制脉冲。 n个输出切换部分中的每一个根据控制脉冲输出与输出切换部分相对应的第一或第二输入信号作为多路复用信号。
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公开(公告)号：US20080170086A1
公开(公告)日：2008-07-17
申请号：US11971865
申请日：2008-01-09
IPC分类号： G09G5/10
CPC分类号： H04N5/361
摘要： (a) The luminance levels of the optical black part pixels included in the output signal of an image sensor are detected and digitized, (b) the digitized luminance levels of the optical black part pixels are averaged, (c) the number of pixels on which averaging is performed is counted, (d) a control signal is generated when the count value of the number of pixels reaches a predetermined value, (e) the black level of the output signal of the image sensor is determined from the averaged luminance level in response to the control signal, and (f) the luminance levels of the effective part pixels included in the output signal of the image sensor whose black level is determined are detected and digitized.
摘要翻译： （a）检测并数字化包括在图像传感器的输出信号中的光学黑色部分像素的亮度级，（b）光学黑色部分像素的数字化亮度级别被平均化，（c） 计算平均值，（d）当像素数量的计数值达到预定值时产生控制信号，（e）从平均亮度级确定图像传感器的输出信号的黑电平 响应于控制信号，并且（f）检测并数字化确定了黑电平的图像传感器的输出信号中包括的有效部分像素的亮度级。
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