公开(公告)号：US08159285B2

公开(公告)日：2012-04-17

申请号：US12729169

申请日：2010-03-22

申请人： Takeshi Hioka ,  Ryu Ogiwara ,  Daisaburo Takashima

发明人： Takeshi Hioka ,  Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G05F1/561

摘要： A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal.

摘要翻译： 根据本发明的实施例的电流供应电路包括具有第一和第二输入端和输出端的运算放大器，具有连接到运算放大器的输出端的控制端的晶体管，并具有第一和第二主端 布置在运算放大器的第一输入端和晶体管的第一主端之间的第一电阻，布置在预定节点和地线之间的第二电阻，所述预定节点位于运算放大器的第一输入端和 第一电阻，第一至第N晶体管，每个具有连接到晶体管的控制端子或第二主端子的控制端子，并且具有输出电流的主端子，其中N为2或更大的整数，以及 第一至第N开关晶体管，其中每个具有主端子，主端子为第一至第N开关 正弦晶体管分别连接到第一至第N晶体管的主端子，提供给相应的第一至第N开关晶体管的控制端的信号的脉冲宽度被设置为恒定，而与信号的脉冲频率无关。

公开(公告)号：US08331191B2

公开(公告)日：2012-12-11

申请号：US13233694

申请日：2011-09-15

申请人： Takeshi Hioka ,  Daisaburo Takashima

发明人： Takeshi Hioka ,  Daisaburo Takashima

IPC分类号： G11C8/00

CPC分类号： G11C16/32 ,  G11C16/30

摘要： According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.

摘要翻译： 根据一个实施例，半导体集成电路器件包括输出电路，该输出电路包括具有第一晶体管的反相器和电流路径串联连接在第一电源电压和第二电源电压之间的第二晶体管，第一二极管电路 其一端连接到第一电源电压，另一端连接到第一晶体管的控制端，以及调节电路，形成用于对第一晶体管的控制端的电荷进行放电的电流通路 当输入时钟处于第一电平时，晶体管到第二电源电压。

公开(公告)号：US08957501B2

公开(公告)日：2015-02-17

申请号：US13671077

申请日：2012-11-07

申请人： Takeshi Hioka ,  Yoshiaki Fukuzumi

发明人： Takeshi Hioka ,  Yoshiaki Fukuzumi

IPC分类号： H01L27/06 ,  H01L27/115 ,  H01L49/02

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L28/88

摘要： A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

摘要翻译： 非易失性半导体存储装置包含存储单元区域，第一电极和第二电极。 存储单元区域形成在衬底上并且包括作为存储器串的一部分堆叠在衬底上的多个存储器单元。 多个第一导电层层叠在基板上。 第一电极用作电容部件一侧的电极，并且包括层叠在基板上的多个导电层，并且与设置在与第一电极相对的电容部件侧的第二电极的层叠导电层水平分离。

公开(公告)号：US20130258796A1

公开(公告)日：2013-10-03

申请号：US13607529

申请日：2012-09-07

申请人： Takeshi Hioka ,  Yoshihisa Iwata

发明人： Takeshi Hioka ,  Yoshihisa Iwata

IPC分类号： G11C5/14

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C5/145 ,  G11C16/10

摘要： A semiconductor device comprising a stacked layer memory block and associated peripheral circuits in stacked layer arrangements. Booster circuits in a variety of stacked layer arrangements are described. The booster circuit possesses plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive the first clock signal on one end, and the other ends are each connected to one end of different rectifier cells. The first capacitor is composed of capacities between plural first conductive layers that are arrayed with a set pitch perpendicularly to the substrate. One of the either even numbered or odd numbered first conductive layers is supplied with a first clock signal. The other of the either even numbered or odd numbered first conductive layers that line perpendicularly to the substrate is, individually, connected to one end of different rectifier cells.

摘要翻译： 一种半导体器件，包括堆叠层存储块和堆叠层布置中的相关外围电路。 描述了各种堆叠层布置中的加强电路。 升压电路具有串联连接的多个整流单元和多个第一电容器。 多个第一电容器在一端接收第一时钟信号，另一端分别连接到不同整流器单元的一端。 第一电容器由以与衬底垂直的设定间距排列的多个第一导电层之间的电容构成。 偶数或奇数编号的第一导电层中的一个被提供有第一时钟信号。 垂直于衬底的偶数或奇数的第一导电层中的另一个单独连接到不同整流器单元的一端。

公开(公告)号：US09070434B2

公开(公告)日：2015-06-30

申请号：US13607529

申请日：2012-09-07

申请人： Takeshi Hioka ,  Yoshihisa Iwata

发明人： Takeshi Hioka ,  Yoshihisa Iwata

IPC分类号： G11C7/22 ,  G11C5/06 ,  G11C5/14 ,  G11C16/10

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C5/145 ,  G11C16/10

摘要： A semiconductor device comprises a stacked layer memory block and associated peripheral circuits, such as a booster circuit, in stacked layer arrangements. The booster circuit includes plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive a first clock signal on one end, and the other ends thereof are each connected to one end of a different rectifier cell. Each first capacitor is composed of plural first conductive layers that are arrayed with a set pitch perpendicular to the substrate. Either the even numbered or the odd numbered first conductive layers are supplied with the first clock signal. The other of the even numbered or odd numbered first conductive layers are each individually connected to one end of a different rectifier cell.

摘要翻译： 半导体器件包括堆叠层存储块和相关联的外围电路，例如叠层层布置中的升压电路。 升压电路包括串联连接的多个整流单元和多个第一电容器。 多个第一电容器在一端接收第一时钟信号，并且其另一端分别连接到不同整流器单元的一端。 每个第一电容器由垂直于衬底的设定间距排列的多个第一导电层组成。 偶数或奇数的第一导电层被提供有第一时钟信号。 偶数或奇数编号的第一导电层中的另一个分别连接到不同整流器单元的一端。

公开(公告)号：US08743611B2

公开(公告)日：2014-06-03

申请号：US13600936

申请日：2012-08-31

申请人： Takeshi Hioka

发明人： Takeshi Hioka

IPC分类号： G11C11/34

CPC分类号： G11C11/40 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor.

摘要翻译： 第一电容器包括多个第一导电层和第二导电层。 第一导电层用作第一电容器的第一电极，第二导电层用作第一电容器的第二电极。 第一导电层和第二导电层在基本上垂直于半导体衬底的方向上交替布置。 控制电路被配置为根据多个存储晶体管的栅极的电压来控制施加到第一导电层和第二导电层中的每一个的电压，从而改变第一电容器的电容。

公开(公告)号：US20130134957A1

公开(公告)日：2013-05-30

申请号：US13427338

申请日：2012-03-22

申请人： Takeshi Hioka

发明人： Takeshi Hioka

IPC分类号： G05F3/02

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0483 ,  H02M3/073 ,  H02M2001/008 ,  H02M2003/077

摘要： A voltage generation circuit according to one embodiment includes a first booster circuit configured to generate a first voltage having a first voltage value, and a second booster circuit group including a plurality of second booster circuits, each second booster circuit configured to generate a second voltage having a second voltage value. The second booster circuits switch to be connected in series and are configured to be capable of generating the first voltage together with the first booster circuit in a change from a first state to a second state.

摘要翻译： 根据一个实施例的电压产生电路包括被配置为产生具有第一电压值的第一电压的第一升压电路和包括多个第二升压电路的第二升压电路组，每个第二升压电路被配置为产生具有 第二电压值。 第二升压电路切换为串联连接，并且被配置为能够与第一升压电路一起产生从第一状态到第二状态的变化中的第一电压。

公开(公告)号：US20130128673A1

公开(公告)日：2013-05-23

申请号：US13424519

申请日：2012-03-20

申请人： Yuri TERADA ,  Dai Nakamura ,  Takeshi Hioka

发明人： Yuri TERADA ,  Dai Nakamura ,  Takeshi Hioka

IPC分类号： G11C16/06

CPC分类号： H01L27/1157 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes memory cells storing data based on respective threshold voltages, having a positive threshold voltage in a data erased state, and includes respective control electrodes. Word lines are selectively electrically connected to the control electrodes of the memory cells, and charged to a potential before writing data to the memory cells. A voltage generator outputs a voltage at an output and includes a first path which discharges the output. A connection circuit is selectively electrically connected to the output of the voltage generator and a first word line, and selectively electrically connects the first word line to a first node which supplies a potential.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元，存储基于相应阈值电压的数据，具有数据擦除状态下的正阈值电压，并且包括相应的控制电极。 字线选择性地电连接到存储单元的控制电极，并且在将数据写入存储单元之前被充电到电位。 电压发生器输出输出端的电压，并包括放电输出的第一路径。 连接电路选择性地电连接到电压发生器和第一字线的输出，并且选择性地将第一字线电连接到提供电位的第一节点。