公开(公告)号：US20090191712A1

公开(公告)日：2009-07-30

申请号：US12208010

申请日：2008-09-10

申请人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

发明人： Kazuyuki HIGASHI ,  Takuji Kuniya ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/308

CPC分类号： H01L21/0273 ,  H01L21/0337 ,  H01L21/0338

摘要： In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.

摘要翻译： 在本发明的一个方面中，制造半导体器件的方法可以包括在待图案化的非晶硅层上形成第一膜，第一膜和非线性膜的线间距比约为3:1 ，在对第一膜进行处理之后，将该图案的线部分从线部分的两个纵向侧线直到线部分的宽度减小到大约三分之一，在下一步处理之后，将非晶硅层的一部分重新形成第一膜 不能使重整部分具有不同的蚀刻比，并除去除了重整部分以外的第一膜和非晶硅层。

公开(公告)号：US08022461B2

公开(公告)日：2011-09-20

申请号：US12468504

申请日：2009-05-19

申请人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

发明人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

IPC分类号： H01L29/76

CPC分类号： H01L23/522 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.

摘要翻译： 半导体器件包括在存储器件区域中以相同的线宽和间距重复排列的多个位线; 与多个位线的平行布置在与该多个位线相同层的多个分流线，并且与存储器件区域中的多个位线的线宽和间距相同; 以及从上层侧配置的上层接触插塞，以便通过在两条或多条分路线上延伸而连接到多条分路线。

公开(公告)号：US08759983B2

公开(公告)日：2014-06-24

申请号：US12361979

申请日：2009-01-29

申请人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

发明人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

IPC分类号： H01L29/41

CPC分类号： H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.

摘要翻译： 根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于 第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

公开(公告)号：US20090206491A1

公开(公告)日：2009-08-20

申请号：US12361979

申请日：2009-01-29

申请人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

发明人： Makoto Wada ,  Akihiro Kajita ,  Kazuyuki Higashi

IPC分类号： H01L23/522

CPC分类号： H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.

摘要翻译： 根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于 第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

公开(公告)号：US08648464B2

公开(公告)日：2014-02-11

申请号：US13413854

申请日：2012-03-07

申请人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

发明人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

IPC分类号： H01L23/48

CPC分类号： H01L21/02639 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/02645 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，公开了一种半导体器件。 该器件包括半导体衬底和半导体衬底上方的互连。 互连包括助催化剂层，助催化剂层上的催化剂层和催化剂层上的石墨烯层。 助催化剂层包括与催化剂层接触的部分。 该部分具有面平面立方结构，其中（111）面平行于半导体衬底的表面定向。 催化剂层具有面平面立方结构，其中（111）面平行于半导体衬底的表面取向。

公开(公告)号：US08482126B2

公开(公告)日：2013-07-09

申请号：US13224929

申请日：2011-09-02

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L23/53276 ,  H01L21/28556 ,  H01L21/76805 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.

摘要翻译： 根据本发明的实施例，一种装置包括基板，形成在基板上或上方的基体，以及一对布线。 基体在平面图中具有线状并沿长度方向延伸。 一对配线包括在基体的长度方向上形成在基体的两侧面上的第一和第二催化剂层，夹着基体; 以及分别以与基体的长度方向接触的方式形成在基体的两侧面上的第一和第二石墨烯层，所述石墨烯层包括垂直层叠的多个石墨烯层 分别相对于基体的两个侧面。

公开(公告)号：US20120080661A1

公开(公告)日：2012-04-05

申请号：US13216435

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L29/15 ,  H01L21/441

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

摘要翻译： 根据一个实施例，石墨烯互连包括绝缘膜，催化剂膜和石墨烯层。 绝缘膜包括互连沟槽。 在互连沟槽中形成催化剂膜并填充互连沟槽的至少一部分。 在互连沟槽中的催化剂膜上形成石墨烯层，并且包括沿垂直于互连沟槽的底表面的方向堆叠的石墨烯片。

公开(公告)号：US20120049370A1

公开(公告)日：2012-03-01

申请号：US13215463

申请日：2011-08-23

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

IPC分类号： H01L23/522 ,  H01L21/768 ,  B82Y99/00

CPC分类号： H01L23/53276 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.

摘要翻译： 根据一个实施例，碳纳米管互连包括第一导电层，绝缘膜，底层催化剂，催化剂失活膜，催化剂膜和碳纳米管。 绝缘膜形成在第一导电层上并包括孔。 在孔的底面上的第一导电层和孔的侧面的绝缘膜上形成催化剂底膜。 在孔中的侧表面上的催化剂底层上形成催化剂失活膜。 在孔的底面的催化剂底层和孔的侧面的催化剂失活膜上形成催化剂膜。 在孔中形成碳纳米管，碳纳米管包括与孔中底表面上的催化剂膜接触的一端。

公开(公告)号：US09159615B2

公开(公告)日：2015-10-13

申请号：US13216435

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

摘要翻译： 根据一个实施例，石墨烯互连包括绝缘膜，催化剂膜和石墨烯层。 绝缘膜包括互连沟槽。 在互连沟槽中形成催化剂膜并填充互连沟槽的至少一部分。 在互连沟槽中的催化剂膜上形成石墨烯层，并且包括沿垂直于互连沟槽的底表面的方向堆叠的石墨烯片。

公开(公告)号：US09117885B2

公开(公告)日：2015-08-25

申请号：US13216445

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/28556 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

摘要翻译： 根据一个实施例，石墨烯互连包括第一绝缘膜，第一催化剂膜和第一石墨烯层。 第一绝缘膜包括互连沟槽。 在互连沟槽的两个侧表面上的第一绝缘膜上形成第一催化剂膜。 第一石墨烯层形成在互连沟槽的两个侧表面上的第一催化剂膜上，并且包括沿垂直于两个侧表面的方向堆叠的石墨烯片。