公开(公告)号：US20060273319A1

公开(公告)日：2006-12-07

申请号：US11442225

申请日：2006-05-30

申请人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

发明人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L29/786 ,  H01L21/46

CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L2221/68354

摘要： It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.

摘要翻译： 本发明的目的在于，制造基板薄型化的集成电路装置时，通过减薄或提高成品率来提高影响生产率的因素，例如电路特性缺陷引起的变化。 在衬底的一个表面上形成阻挡层，并且在阻挡层上形成元件，然后从其另一个表面减薄衬底。 将基板研磨或抛光的方法或其中通过化学反应蚀刻基板的方法用作薄膜或去除基板的方法。

公开(公告)号：US07928554B2

公开(公告)日：2011-04-19

申请号：US11667072

申请日：2005-11-04

申请人： Naoto Kusumoto ,  Takuya Tsurume

发明人： Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L23/48

CPC分类号： H01Q1/2208 ,  G06K19/07749 ,  H01L23/49855 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01Q7/00 ,  Y10T29/49016 ,  Y10T29/49018 ,  H01L2924/00

摘要： An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by stacking a conductive film 11, a resin film 13, an integrated circuit 12, and a resin film 14 are rolled so that the resin film 14 is outside. Then, the laminated body is integrated in a roll form by softening the resin films 13, 14 by applying heat. By slicing the rolled laminated body along with the direction in which the rolled conductive film 31 appears in the cross section, an IC chip with antenna formed by the rolled conductive film 11 is formed.

摘要翻译： 公开了用于ID芯片等的天线，其具有平坦化的天线不均匀性，并且公开了具有平坦表面的天线的IC芯片。 制造安装有天线的集成电路变得容易。 通过层叠导电膜11，树脂膜13，集成电路12和树脂膜14而形成的层叠体被卷成树脂膜14的外侧。 然后，通过施加热量使树脂膜13,14软化，将层叠体整合成卷状。 通过将轧制的层压体与轧制导电膜31在横截面中出现的方向切片，形成由卷绕的导电膜11形成的具有天线的IC芯片。

公开(公告)号：US07820495B2

公开(公告)日：2010-10-26

申请号：US11448053

申请日：2006-06-07

申请人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

发明人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L27/1266 ,  H01L27/1285 ,  H01L27/1292

摘要： An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate.

摘要翻译： 本发明的目的是提供一种用于制造半导体器件的方法，其中，即使在形成半导体元件之后减薄或去除衬底的情况下，也可以抑制由于杂质元素，水分等的进入而对半导体元件的影响 在基板上。 特征在于，在基板的至少一面上形成作为保护膜的绝缘膜，在基板上进行表面处理，在绝缘膜上形成薄膜晶体管等半导体元件，并使基板 。 作为表面处理，在基板上进行杂质元素或等离子体处理的添加。 作为使基板变薄的方法，可以在基板的另一侧进行研磨处理，研磨处理等来部分除去基板。

公开(公告)号：US20060270236A1

公开(公告)日：2006-11-30

申请号：US11435804

申请日：2006-05-18

申请人： Naoto Kusumoto ,  Takuya Tsurume

发明人： Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L29/04 ,  H01L21/461 ,  C03C15/00 ,  H01L31/036

CPC分类号： H01L27/1266 ,  H01L27/1214

摘要： To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate.

摘要翻译： 为了提供与传统的玻璃基板或单晶硅基板不同的低成本且薄型的薄膜集成电路，其适用于批量生产，以及薄膜集成电路器件或IC芯片的结构和工艺 具有薄膜集成电路。 半导体器件的制造方法包括以下步骤：在硅衬底的一个表面上形成第一绝缘膜，在第一绝缘膜上形成具有至少两个薄膜集成电路的层，形成树脂层以覆盖 层，具有薄膜集成电路，形成膜以覆盖树脂层，研磨由具有薄膜集成电路的层形成的硅衬底的一个表面的背面，并且研磨硅的表面 基质。

公开(公告)号：US07791153B2

公开(公告)日：2010-09-07

申请号：US12371937

申请日：2009-02-17

申请人： Takuya Tsurume ,  Naoto Kusumoto

发明人： Takuya Tsurume ,  Naoto Kusumoto

IPC分类号： H01L27/14 ,  H01L31/00 ,  G06K19/06 ,  G08B13/14

CPC分类号： G06K19/07749

摘要： It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate; a hole having curvature is formed in part of one surface side of the substrate; the substrate is thinned (for example, the other surface of the substrate is ground and polished); and the substrate is cut off so that a cross section of the substrate has curvature corresponding to a portion where the hole is formed; whereby a laminated body including an integrated circuit is formed. Further, a thickness of the substrate, which is polished, is 2 μm or more and 50 μm or less.

摘要翻译： 本发明的一个目的是提供一种柔性和优异的物理强度的半导体器件的制造方法。 作为制造半导体器件的方法，在衬底的一个表面上形成包括多个集成电路的元件层; 在基板的一个表面侧的一部分上形成具有曲率的孔; 衬底变薄（例如，衬底的另一表面被研磨和抛光）; 并且基板被切断，使得基板的横截面具有与形成孔的部分相对应的曲率; 从而形成包括集成电路的层叠体。 此外，被研磨的基板的厚度为2μm以上且50μm以下。

公开(公告)号：US07465596B2

公开(公告)日：2008-12-16

申请号：US11454851

申请日：2006-06-19

申请人： Takuya Tsurume ,  Naoto Kusumoto

发明人： Takuya Tsurume ,  Naoto Kusumoto

IPC分类号： H01L21/00

CPC分类号： H01L21/67132 ,  H01L21/78

摘要： To provide a semiconductor device including a thinned substrate with high yield. After forming a protective layer in a predetermined portion (at least a portion covering a side surface of a substrate) of the substrate, grinding and polishing of the substrate are performed. In other words, an element layer including a plurality of integrated circuits is formed over one surface of the substrate, the protective layer is formed in contact with at least the side surface of the substrate, and the substrate is thinned (for example, the other surface of the substrate is ground and polished), the protective layer is removed, and the polished substrate and the element layer is divided so as to form stack bodies including a layer provided with at least one of the plurality of integrated circuits.

摘要翻译： 以高产率提供包括薄化基板的半导体器件。 在基板的规定部（覆盖基板的侧面的至少一部分）上形成保护层后，进行基板的研磨和研磨。 换句话说，在基板的一个表面上形成包括多个集成电路的元件层，保护层至少形成为与基板的侧表面接触，并且使基板变薄（例如，另一个 将衬底的表面研磨抛光），除去保护层，并且将抛光的衬底和元件层分开以形成包括设置有多个集成电路中的至少一个的层的堆叠体。

公开(公告)号：US20060055014A1

公开(公告)日：2006-03-16

申请号：US11213997

申请日：2005-08-30

申请人： Takuya Tsurume ,  Koji Dairiki ,  Naoto Kusumoto

发明人： Takuya Tsurume ,  Koji Dairiki ,  Naoto Kusumoto

IPC分类号： H01L23/02 ,  H01L23/24

CPC分类号： H01L21/6835 ,  H01L23/20 ,  H01L23/22 ,  H01L23/58 ,  H01L24/83 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention provides a new type wireless chip that can be used without being fixed on a product. Specifically, a wireless chip can have a new function by a sealing step. One feature of a wireless chip according to the present invention is to have a structure in which an integrated circuit is sealed by films. In particular, the films sealing the integrated circuit have a hollow structure; therefore the wireless chip can have a new function.

摘要翻译： 本发明提供了一种新型无线芯片，可以在不固定在产品上的情况下使用。 具体地说，无线芯片可以通过密封步骤具有新的功能。 根据本发明的无线芯片的一个特征是具有其中集成电路被膜密封的结构。 特别地，密封集成电路的膜具有中空结构; 因此无线芯片可以具有新功能。

公开(公告)号：US07972910B2

公开(公告)日：2011-07-05

申请号：US11442225

申请日：2006-05-30

申请人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

发明人： Koji Dairiki ,  Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L21/46

CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L2221/68354

摘要： It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.

摘要翻译： 本发明的目的在于，制造基板薄型化的集成电路装置时，通过减薄或提高成品率来提高影响生产率的因素，例如电路特性缺陷引起的变化。 在衬底的一个表面上形成阻挡层，并且在阻挡层上形成元件，然后从其另一个表面减薄衬底。 将基板研磨或抛光的方法或其中通过化学反应蚀刻基板的方法用作薄膜或去除基板的方法。

公开(公告)号：US07728383B2

公开(公告)日：2010-06-01

申请号：US12260107

申请日：2008-10-29

申请人： Naoto Kusumoto ,  Takuya Tsurume

发明人： Naoto Kusumoto ,  Takuya Tsurume

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L27/12

CPC分类号： H01L27/1266 ,  H01L27/1214

摘要： To provide a thin film integrated circuit at low cost and with thin thickness, which is applicable to mass production unlike the conventional glass substrate or the single crystalline silicon substrate, and a structure and a process of a thin film integrated circuit device or an IC chip having the thin film integrated circuit. A manufacturing method of a semiconductor device includes the steps of forming a first insulating film over one surface of a silicon substrate, forming a layer having at least two thin film integrated circuits over the first insulating film, forming a resin layer so as to cover the layer having the thin film integrated circuit, forming a film so as to cover the resin layer, grinding a backside of one surface of the silicon substrate which is formed with the layer having the thin film integrated circuit, and polishing the ground surface of the silicon substrate.

摘要翻译： 为了提供与传统的玻璃基板或单晶硅基板不同的低成本且薄型的薄膜集成电路，其适用于批量生产，以及薄膜集成电路器件或IC芯片的结构和工艺 具有薄膜集成电路。 半导体器件的制造方法包括以下步骤：在硅衬底的一个表面上形成第一绝缘膜，在第一绝缘膜上形成具有至少两个薄膜集成电路的层，形成树脂层以覆盖 层，具有薄膜集成电路，形成膜以覆盖树脂层，研磨由具有薄膜集成电路的层形成的硅衬底的一个表面的背面，并且研磨硅的表面 基质。

公开(公告)号：US07510950B2

公开(公告)日：2009-03-31

申请号：US11454878

申请日：2006-06-19

申请人： Takuya Tsurume ,  Naoto Kusumoto

发明人： Takuya Tsurume ,  Naoto Kusumoto

IPC分类号： H01L21/78 ,  H01L21/46 ,  H01L21/301 ,  H01L21/30 ,  G06K19/06

CPC分类号： G06K19/07749

摘要： It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is flexible and superiority in physical strength. As a method for manufacturing a semiconductor device, an element layer including a plurality of integrated circuits is formed over one surface of a substrate; a hole having curvature is formed in part of one surface side of the substrate; the substrate is thinned (for example, the other surface of the substrate is ground and polished); and the substrate is cut off so that a cross section of the substrate has curvature corresponding to a portion where the hole is formed; whereby a laminated body including an integrated circuit is formed. Further, a thickness of the substrate, which is polished, is 2 μm or more and 50 μm or less.

摘要翻译： 本发明的一个目的是提供一种柔性和优异的物理强度的半导体器件的制造方法。 作为制造半导体器件的方法，在衬底的一个表面上形成包括多个集成电路的元件层; 在基板的一个表面侧的一部分上形成具有曲率的孔; 衬底变薄（例如，衬底的另一表面被研磨和抛光）; 并且基板被切断，使得基板的横截面具有与形成孔的部分相对应的曲率; 从而形成包括集成电路的层叠体。 此外，抛光的基板的厚度为2μm以上且50μm以下。