公开(公告)号：US12087729B2

公开(公告)日：2024-09-10

申请号：US17406097

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Yuan Chang

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/20 ,  H01L23/24 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/56 ,  H01L23/20 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/315 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181

Abstract: A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

公开(公告)号：US11876007B2

公开(公告)日：2024-01-16

申请号：US17651612

申请日：2022-02-18

Applicant: Infineon Technologies AG

Inventor： Rainer Markus Schaller ,  Horst Theuss

IPC: H01L21/673 ,  H01L23/049 ,  H01L23/20 ,  H01L21/67 ,  B81C1/00

CPC classification number: H01L21/67376 ,  B81C1/00285 ,  H01L21/67126 ,  H01L21/67393 ,  H01L23/049 ,  H01L23/20 ,  B81C2203/0145

Abstract: A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

公开(公告)号：US11742325B2

公开(公告)日：2023-08-29

申请号：US17462032

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jen-Yuan Chang ,  Tzu-Chung Tsai

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/20 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/20 ,  H01L23/3185 ,  H01L23/3192 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/291 ,  H01L24/32 ,  H01L2224/32145

Abstract: A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.

公开(公告)号：US09922894B1

公开(公告)日：2018-03-20

申请号：US15269629

申请日：2016-09-19

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla ,  David Abdo ,  Mali Mahalingam ,  Carl D'Acosta

IPC: H01L23/12 ,  H01L23/66 ,  H01L23/20 ,  H01L23/047 ,  H01L21/48 ,  H01L23/057 ,  H01L23/367 ,  B22F3/10 ,  B22F1/00 ,  B23K35/02 ,  B23K35/30 ,  H01L23/00

CPC classification number: H01L23/20 ,  B22F1/0062 ,  B22F3/10 ,  B22F5/10 ,  B22F7/02 ,  B22F2301/10 ,  B22F2301/255 ,  B22F2302/45 ,  B23K35/025 ,  B23K35/30 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/047 ,  H01L23/057 ,  H01L23/10 ,  H01L23/3675 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/73265 ,  H01L2924/01042 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

公开(公告)号：US20180053702A1

公开(公告)日：2018-02-22

申请号：US15792225

申请日：2017-10-24

Applicant: Erick Merle Spory

Inventor： Erick Merle Spory

IPC: H01L23/20 ,  H01L23/00 ,  H01L21/48 ,  H01L23/04 ,  H01L23/495 ,  H01L23/498 ,  H01L21/50 ,  H01L23/26

CPC classification number: H01L23/20 ,  H01L21/4803 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/10 ,  H01L23/26 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49861 ,  H01L23/564 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24175 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/2731 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73267 ,  H01L2224/82102 ,  H01L2224/82103 ,  H01L2224/82214 ,  H01L2224/82815 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3656 ,  H01L2924/3861

Abstract: A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

公开(公告)号：US20180040529A1

公开(公告)日：2018-02-08

申请号：US15792381

申请日：2017-10-24

Applicant: Erick Merle Spory

Inventor： Erick Merle Spory

IPC: H01L23/20 ,  H01L21/48 ,  H01L23/04 ,  H01L23/498 ,  H01L21/50 ,  H01L23/26 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/20 ,  H01L21/4803 ,  H01L21/4817 ,  H01L21/4867 ,  H01L21/50 ,  H01L23/04 ,  H01L23/057 ,  H01L23/10 ,  H01L23/26 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/564 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24175 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/2731 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/82102 ,  H01L2224/82103 ,  H01L2224/82214 ,  H01L2224/82815 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3656 ,  H01L2924/3861

Abstract: An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

公开(公告)号：US20170186731A1

公开(公告)日：2017-06-29

申请号：US15166038

申请日：2016-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Atsuyoshi Koike

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/02 ,  H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/20 ,  H01L23/467 ,  H01L23/473 ,  G11C29/04 ,  G11C16/04 ,  H01L25/00

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C16/0483 ,  G11C29/04 ,  G11C29/765 ,  G11C2029/0403 ,  H01L23/02 ,  H01L23/20 ,  H01L23/3675 ,  H01L23/467 ,  H01L23/473 ,  H01L23/481 ,  H01L24/14 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: An SSD with a package optimized for semiconductor wafers is configured by thinning a plurality of undiced wafers and stacking the wafers. The wafers are connected to each other by TSV. A subset of the wafers include memory circuits. One of the wafer not in the subset includes peripheral circuits. A casing houses the wafers.

公开(公告)号：US20160126623A1

公开(公告)日：2016-05-05

申请号：US14931720

申请日：2015-11-03

Applicant: RF Micro Devices, Inc.

Inventor： George Maxim ,  Dirk Robert Walter Leipold ,  Marcus Granger-Jones ,  Baker Scott

IPC: H01Q1/50

CPC classification number: H01L23/315 ,  H01L21/02266 ,  H01L21/02282 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/20 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3737 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/562 ,  H01L24/17 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01Q1/50 ,  H05K1/0203 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Antenna aperture tuning circuitry includes a first signal path and a second signal path coupled in parallel between an antenna radiating element and ground. A first LC resonator and a second LC resonator are each coupled between the first signal path and ground. The first LC resonator and the second LC resonator are electromagnetically coupled such that a coupling factor between the first LC resonator and the second LC resonator is between about 1.0% and 40.0%. A third LC resonator and a fourth LC resonator are each coupled between the second signal path and ground. The third LC resonator and the fourth LC resonator are electromagnetically coupled such that a coupling factor between the third LC resonator and the fourth LC resonator is between about 1.0% and 40.0%.

Abstract translation: 天线孔径调谐电路包括在天线辐射元件和地之间并联耦合的第一信号路径和第二信号路径。 第一LC谐振器和第二LC谐振器各自耦合在第一信号路径和地之间。 第一LC谐振器和第二LC谐振器被电磁耦合，使得第一LC谐振器和第二LC谐振器之间的耦合因子在约1.0％和40.0％之间。 第三LC谐振器和第四LC谐振器各自耦合在第二信号路径和地之间。 第三LC谐振器和第四LC谐振器被电磁耦合，使得第三LC谐振器和第四LC谐振器之间的耦合因子在约1.0％和40.0％之间。

公开(公告)号：US08237171B2

公开(公告)日：2012-08-07

申请号：US12658576

申请日：2010-02-09

Applicant: Tracy Autry

Inventor： Tracy Autry

IPC: H01L29/15

CPC classification number: H01L23/20 ,  H01L23/051 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.

Abstract translation: 一种密封的集成电路封装，其包括容纳半导体管芯的腔体，由此在组装期间和形成时腔体被加压。 本发明防止了当封装在大气压下经受高温然后在高电压下降低管芯的性能而被冷却时产生的封装上的应力。 通过在具有惰性气体的气氛中在高压（例如高达50PSIG）下封装模具，并且在完成的封装中提供大的压力，模具在较高的电压下显着地不太可能发生电弧，从而允许实现 单片封装最多可操作至少1200伏。 此外，本发明被配置为使用与可在较高温度下处理的碳化硅模具相容的钎焊元件。

公开(公告)号：US20100270667A1

公开(公告)日：2010-10-28

申请号：US12429541

申请日：2009-04-24

Applicant: Chong Yee Tong ,  Hui Teng Wang

Inventor： Chong Yee Tong ,  Hui Teng Wang

IPC: H01L23/20 ,  H01L23/498 ,  H01L21/98

CPC classification number: H01L23/055 ,  H01L23/20 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16172 ,  H01L2924/16747 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the metal cap.

Abstract translation: 半导体封装包括第一半导体芯片，第二半导体芯片，第一基板，第二基板和金属盖。 芯片电连接到第一基板，第二基板设置在芯片之间，并且芯片和第二基板设置在金属盖内。