公开(公告)号：US07419874B2

公开(公告)日：2008-09-02

申请号：US11330402

申请日：2006-01-12

申请人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

发明人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

IPC分类号： H01L21/8242

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L28/40

摘要： The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

摘要翻译： 本发明是为了防止具有形成在同一半导体衬底上的电容器和MOS晶体管的半导体器件中的电容器的电介质击穿。 在P型半导体衬底的整个表面上形成作为高电压MOS晶体管的栅极绝缘膜的SiO 2膜。 在高电压MOS晶体管形成区域和覆盖与电容器形成区域相邻的沟槽隔离膜的边缘的SiO 2膜的一部分上选择性地形成光致抗蚀剂层，并且SiO 2 使用该光致抗蚀剂层作为掩模通过蚀刻除去膜。 由于在该蚀刻中光致抗蚀剂层用作掩模，所以与电容器相邻的沟槽隔离膜的边缘不被切割得太深。 在该蚀刻中残留的SiO 2膜和之后形成的SiO 2膜形成电容器绝缘膜。

公开(公告)号：US20060172488A1

公开(公告)日：2006-08-03

申请号：US11330402

申请日：2006-01-12

申请人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

发明人： Tatsuya Fujishima ,  Mikio Fukuda ,  Yuji Tsukada ,  Keiji Ogata ,  Izuo Iida

IPC分类号： H01L21/8242

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L28/40

摘要： The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

摘要翻译： 本发明是为了防止具有形成在同一半导体衬底上的电容器和MOS晶体管的半导体器件中的电容器的电介质击穿。 在P型半导体衬底的整个表面上形成作为高电压MOS晶体管的栅极绝缘膜的SiO 2膜。 在高电压MOS晶体管形成区域和覆盖与电容器形成区域相邻的沟槽隔离膜的边缘的SiO 2膜的一部分上选择性地形成光致抗蚀剂层，并且SiO 2 使用该光致抗蚀剂层作为掩模通过蚀刻除去膜。 由于在该蚀刻中光致抗蚀剂层用作掩模，所以与电容器相邻的沟槽隔离膜的边缘不被切割得太深。 在该蚀刻中残留的SiO 2膜和之后形成的SiO 2膜形成电容器绝缘膜。

公开(公告)号：US20060113584A1

公开(公告)日：2006-06-01

申请号：US11267582

申请日：2005-11-07

申请人： Mikio Fukuda ,  Tatsuya Fujishima

发明人： Mikio Fukuda ,  Tatsuya Fujishima

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42324

摘要： The first polysilicon film is formed on the semiconductor substrate with the gate insulation film between them. The second silicon nitride film with the first opening is further formed and the first polysilicon film is etched using the second silicon nitride film as a mask. Then, the spacer film with the second opening is formed at the first opening. The oxidation prevention layer is formed through the first anneal processing performed in ammonia atmosphere. Then, the source region, the source line, the source line cap film, the floating gate, the tunnel insulation film, the control gate, and the drain region are formed.

摘要翻译： 第一多晶硅膜形成在半导体衬底上，栅绝缘膜在它们之间。 进一步形成具有第一开口的第二氮化硅膜，并且使用第二氮化硅膜作为掩模蚀刻第一多晶硅膜。 然后，在第一开口处形成具有第二开口的间隔膜。 通过在氨气氛中进行的第一退火处理形成氧化防止层。 然后，形成源极区域，源极线，源极线帽膜，浮动栅极，隧道绝缘膜，控制栅极和漏极区域。

公开(公告)号：US06849550B2

公开(公告)日：2005-02-01

申请号：US10190756

申请日：2002-07-09

申请人： Yoshinari Ichihashi ,  Norihiro Ikeda ,  Takashi Gotou ,  Ryousuke Usui ,  Tatsuya Fujishima

发明人： Yoshinari Ichihashi ,  Norihiro Ikeda ,  Takashi Gotou ,  Ryousuke Usui ,  Tatsuya Fujishima

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/485

摘要： A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.

摘要翻译： 即使半导体器件设计为高度集成，也可以形成具有高电可靠性的连接孔的半导体器件的制造方法。 半导体器件包括下层布线和层间绝缘膜，其形成在下层布线上并具有与下层布线连接的连接孔。 该方法包括通过蚀刻层间绝缘膜形成连接孔。 在第一蚀刻条件下，至少在下层布线附近通过物理反应蚀刻下层布线的一部分，并且在保证选择性的第二蚀刻条件下蚀刻层间绝缘膜的一部分，形成连接孔 相对于下层布线的比例。

公开(公告)号：US07224038B2

公开(公告)日：2007-05-29

申请号：US09985743

申请日：2001-11-06

申请人： Ryosuke Usui ,  Tatsuya Fujishima

发明人： Ryosuke Usui ,  Tatsuya Fujishima

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/3065

摘要： A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface and an element isolation trench formed on the main surface of the semiconductor device, while the trench width of an upper end of the element isolation trench is larger than the trench width of a bottom surface and the length of a side surface located between the upper end and an end of the bottom surface is larger than the length of a straight line connecting the upper end and the end of the bottom surface. Thus, the element isolation trench is so formed that the trench width of the upper end is larger than the trench width of the bottom surface, whereby an insulator can be readily embedded in the element isolation trench. Thus, the insulator can be prevented from defective embedding. Further, the element isolation trench is so formed that the length of the side surface located between the upper end and the end of the bottom surface is larger than the length of the straight line connecting the upper end and the end of the bottom surface, thereby improving the withstand voltage of the element isolation region as compared with a case of forming the side surface located between the upper end and the end of the bottom surface in a tapered manner.

摘要翻译： 可以获得能够防止绝缘体的嵌入不良和提高元件隔离区域的耐电压（绝缘强度）的半导体装置。 该半导体器件包括半导体衬底，其具有形成在半导体器件的主表面上的主表面和元件隔离沟槽，而元件隔离沟槽的上端的沟槽宽度大于底表面的沟槽宽度， 位于底表面的上端和端部之间的侧表面的长度大于连接底表面的上端和端部的直线的长度。 因此，元件隔离沟槽被形成为使得上端的沟槽宽度大于底表面的沟槽宽度，由此绝缘体可以容易地嵌入元件隔离沟槽中。 因此，能够防止绝缘体的嵌入不良。 此外，元件隔离沟槽被形成为使得位于底表面的上端和端部之间的侧表面的长度大于连接底表面的上端和端部的直线的长度，从而 与以锥形方式形成位于底表面的上端和端部之间的侧表面的情况相比，提高了元件隔离区域的耐受电压。

公开(公告)号：US20110125075A1

公开(公告)日：2011-05-26

申请号：US11988832

申请日：2006-07-14

申请人： Yoshifumi Takei ,  Kenji Kadomatsu ,  Tatsuya Fujishima ,  Takashi Muramatsu

发明人： Yoshifumi Takei ,  Kenji Kadomatsu ,  Tatsuya Fujishima ,  Takashi Muramatsu

IPC分类号： A61N1/30 ,  A01K67/027 ,  C12Q1/02

CPC分类号： A61N1/327 ,  A61K31/7088 ,  A61K38/1866 ,  A61K48/00 ,  A61N1/0424 ,  C12N15/111 ,  C12N15/1136 ,  C12N2310/14 ,  C12N2320/32 ,  C12N2320/51 ,  G01N33/5088

摘要： A method for controlling an electroporation apparatus for use in an animal such as human and a non-human animal, the method comprising a step of applying a voltage to an electrode of the electroporation apparatus placed in/on a biological sample of the animal in the presence of a nucleic acid construct capable of inhibiting the expression of a gene in the animal. In this manner, a nucleic acid construct can be introduced into a cell of a living body with good efficiency.

摘要翻译： 一种用于控制动物如人和非人动物的电穿孔装置的方法，所述方法包括向放置在动物生物样品中的电穿孔装置的电极施加电压的步骤 能够抑制动物中基因表达的核酸构建体的存在。 以这种方式，可以以高效率将核酸构建体引入生物体的细胞。

公开(公告)号：US07066786B2

公开(公告)日：2006-06-27

申请号：US10941083

申请日：2004-09-15

申请人： Tatsuya Fujishima ,  Katsumi Sameshima

发明人： Tatsuya Fujishima ,  Katsumi Sameshima

IPC分类号： B24B53/00

CPC分类号： B24B53/017 ,  B24B49/12

摘要： A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.

摘要翻译： 提供了一种用于对抛光垫的表面进行非破坏性监测来定量检测抛光垫的修整的最佳终点的方法。 抛光垫被修整预定时间，并且用由激光聚焦位移计制成的光学测量装置测量抛光垫的表面的粗糙度。 然后，获得表示抛光垫的表面粗糙度与修整时间之间的相关性的特性曲线。 获得表面粗糙度与修整时间特性曲线的梯度。 当梯度达到预定的梯度值时，停止敷料。 重复这些步骤，直到表面粗糙度与敷料时间特性曲线的梯度达到预定的梯度值。

公开(公告)号：US20050090185A1

公开(公告)日：2005-04-28

申请号：US10941083

申请日：2004-09-15

申请人： Tatsuya Fujishima ,  Katsumi Sameshima

发明人： Tatsuya Fujishima ,  Katsumi Sameshima

IPC分类号： B24B53/00 ,  B24B49/12 ,  B24B53/007 ,  B24B53/017 ,  B24B53/02 ,  H01L21/304 ,  B24B49/00

CPC分类号： B24B53/017 ,  B24B49/12

摘要： A method to quantitatively detect an optimum endpoint of dressing of a polishing pad with a non-destructive monitoring of a surface of the polishing pad is offered. The polishing pad is dressed for a predetermined period, and roughness of the surface of the polishing pad is measured with an optical measurement device made of a laser focus displacement meter. Then a characteristic curve representing a correlation between surface roughness of the polishing pad and dressing time is obtained. A gradient of the surface roughness versus dressing time characteristic curve is obtained. Dressing is stopped when the gradient reaches a predetermined value of gradient. These steps are repeated until the gradient of the surface roughness versus dressing time characteristic curve reaches the predetermined value of gradient.

摘要翻译： 提供了一种用于对抛光垫的表面进行非破坏性监测来定量检测抛光垫的修整的最佳终点的方法。 抛光垫被修整预定时间，并且用由激光聚焦位移计制成的光学测量装置测量抛光垫的表面的粗糙度。 然后，获得表示抛光垫的表面粗糙度与修整时间之间的相关性的特性曲线。 获得表面粗糙度与修整时间特性曲线的梯度。 当梯度达到预定的梯度值时，停止敷料。 重复这些步骤，直到表面粗糙度与修整时间特性曲线的梯度达到预定的梯度值。