公开(公告)号：US06462374B2

公开(公告)日：2002-10-08

申请号：US09814000

申请日：2001-03-22

申请人： Tatsuya Usuki ,  Naoto Horiguchi

发明人： Tatsuya Usuki ,  Naoto Horiguchi

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

摘要： To provide a semiconductor device which can retain information for a long period of time even in a case that the tunnel insulation film is thin. A semiconductor device comprises a first insulation film 14 formed on a semiconductor substrate 10, a floating gate electrode 22 formed on the first insulation film, a second insulation 24 film formed on the floating gate electrode, and a control gate electrode 26 formed on the second insulation film. A depletion layer is formed in the floating gate electrode near the first insulation film in a state that no voltage is applied between the floating gate electrode and the semiconductor substrate.

摘要翻译： 即使在隧道绝缘膜薄的情况下，也能够长时间地保持信息的半导体装置。 半导体器件包括形成在半导体衬底10上的第一绝缘膜14，形成在第一绝缘膜上的浮栅电极22，形成在浮栅电极上的第二绝缘层24，以及形成在第二绝缘膜上的控制栅极26 绝缘膜。 在浮置栅电极和半导体基板之间没有施加电压的状态下，在第一绝缘膜附近的浮置栅电极中形成耗尽层。

公开(公告)号：US06815759B2

公开(公告)日：2004-11-09

申请号：US09726386

申请日：2000-12-01

申请人： Naoto Horiguchi ,  Tatsuya Usuki ,  Kenichi Goto

发明人： Naoto Horiguchi ,  Tatsuya Usuki ,  Kenichi Goto

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  G11C16/0416 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7883

摘要： A tunneling insulating film is formed on the partial surface area of a semiconductor substrate. A floating gate electrode is formed on the tunneling insulating film. A gate insulating film covers the side wall of the floating gate electrode and a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A first control gate electrode is disposed on the gate insulating film over the side wall of the floating gate electrode and over a partial surface area of the semiconductor substrate on both sides of the floating gate electrode. A pair of impurity doped regions is formed in a surface layer of the semiconductor substrate on both sides of a gate structure including the floating gate structure and first control gate structure.

公开(公告)号：US07768692B2

公开(公告)日：2010-08-03

申请号：US11633537

申请日：2006-12-05

申请人： Kazuya Takemoto ,  Tatsuya Usuki ,  Yasuhiko Arakawa

发明人： Kazuya Takemoto ,  Tatsuya Usuki ,  Yasuhiko Arakawa

IPC分类号： G02F1/1335 ,  H04L9/08

CPC分类号： H04B10/70 ,  G02F1/37 ,  H04L9/0858

摘要： A single-photon generator includes a single-photon generating device generating a single-photon pulse having a wavelength on the shorter wavelength side than a communication wavelength band, and a single-photon wavelength conversion device performing wavelength conversion of the single-photon pulse into a single-photon pulse of the communication wavelength band, using pump pulse light for single-photon wavelength conversion.

摘要翻译： 单光子发生器包括产生具有比通信波长带更短波长侧的波长的单光子脉冲的单光子产生装置，以及执行单光子脉冲的波长转换的单光子波长转换装置 通信波长带的单光子脉冲，使用泵浦脉冲光进行单光子波长转换。

公开(公告)号：US07700937B2

公开(公告)日：2010-04-20

申请号：US11522421

申请日：2006-09-18

申请人： Shinichi Hirose ,  Motomu Takatsu ,  Tatsuya Usuki ,  Yasuhiko Arakawa

发明人： Shinichi Hirose ,  Motomu Takatsu ,  Tatsuya Usuki ,  Yasuhiko Arakawa

IPC分类号： H01L33/00

CPC分类号： H01L31/035281 ,  H01L31/02327 ,  H01L31/03046 ,  H01L33/20 ,  H01S5/0201 ,  Y02E10/50 ,  Y10S977/949 ,  Y10S977/95

摘要： A single-photon generating device is configured to have a solid substrate including abase portion, and a pillar portion which is formed on the surface side of the base portion with a localized level existent in the vicinity of the tip of the base portion. The above pillar portion is formed to have a larger cross section on the base portion side than the cross section on the tip side, so that the light generated from the localized level is reflected on the surface, propagated inside the pillar portion, and output from the back face side of the base portion.

摘要翻译： 单光子产生装置被配置为具有包括基部的固体基板，并且在基部的尖端附近存在形成有位于基部的表面侧的柱部。 上述柱部形成为在基部侧的截面比前端侧的截面大的截面，使得从局部水平产生的光在表面上反射，在柱部内传播，并从 基部的背面侧。

公开(公告)号：US07432153B2

公开(公告)日：2008-10-07

申请号：US11898685

申请日：2007-09-14

申请人： Kouji Tsunoda ,  Tatsuya Usuki

发明人： Kouji Tsunoda ,  Tatsuya Usuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.

摘要翻译： 直接隧道半导体存储器件包括形成在半导体衬底上的器件隔离结构，包括器件隔离沟槽和填充器件隔离沟槽的器件隔离绝缘膜，覆盖两个侧壁表面的电介质膜和浮动栅极的顶表面 形成在所述半导体基板上的电极，经由所述电介质膜设置在所述浮栅电极的侧壁面上的导电部，构成控制栅电极的一部分的导体部，以及形成在所述第一扩散区 浮置栅电极，其中所述第一和第二扩散区形成在所述器件隔离槽的表面上，偏离所述浮置栅电极正下方的区域，所述导电部分形成在所述器件区域中，偏离所述器件隔离沟槽。

公开(公告)号：US20080057648A1

公开(公告)日：2008-03-06

申请号：US11898685

申请日：2007-09-14

申请人： Kouji Tsunoda ,  Tatsuya Usuki

发明人： Kouji Tsunoda ,  Tatsuya Usuki

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.

公开(公告)号：US07288813B2

公开(公告)日：2007-10-30

申请号：US11012277

申请日：2004-12-16

申请人： Kouji Tsunoda ,  Tatsuya Usuki

发明人： Kouji Tsunoda ,  Tatsuya Usuki

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A direct-tunneling semiconductor memory device includes a device isolation structure formed on a semiconductor substrate, including a device isolation trench and a device isolation insulation film filling the device isolation trench, a dielectric film covering both sidewall surfaces and a top surface of a floating gate electrode formed on the semiconductor substrate, a conductive part provided on the sidewall surfaces of the floating gate electrode via the dielectric film, the conductor part constituting a part of a control gate electrode, and first and second diffusion regions formed at respective lateral sides of the floating gate electrode, wherein the first and second diffusion regions are formed on a surface of the device isolation groove with offset from a region right underneath the floating gate electrode, the conductive part is formed in the device region with offset from the device isolation trench.

摘要翻译： 直接隧道半导体存储器件包括形成在半导体衬底上的器件隔离结构，包括器件隔离沟槽和填充器件隔离沟槽的器件隔离绝缘膜，覆盖两个侧壁表面的电介质膜和浮动栅极的顶表面 形成在所述半导体基板上的电极，经由所述电介质膜设置在所述浮栅电极的侧壁面上的导电部，构成控制栅电极的一部分的导体部，以及形成在所述第一扩散区 浮置栅电极，其中所述第一和第二扩散区形成在所述器件隔离槽的表面上，偏离所述浮置栅电极正下方的区域，所述导电部分形成在所述器件区域中，偏离所述器件隔离沟槽。

公开(公告)号：US07288811B2

公开(公告)日：2007-10-30

申请号：US11037176

申请日：2005-01-19

申请人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

发明人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/0692 ,  H01L29/7883

摘要： A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

摘要翻译： 半导体器件具有形成在半导体衬底上的隔离区域，并且限定包括选择晶体管区域和直接隧道元件区域的连续有源区域; 形成在所述选择晶体管区域的沟道区上的栅极绝缘膜; 隧道绝缘膜，其形成在所述直接隧道元件区域的部分区域上，并且具有与所述栅极绝缘膜的厚度不同的厚度; 形成在栅极绝缘膜和隧道绝缘膜上方的连续浮栅; 形成在所述浮栅电极的表面上的电极间绝缘膜; 通过所述电极间绝缘膜与所述浮栅相对的控制栅电极; 以及形成在选择晶体管区域的沟道区域的两侧并且不与隧道绝缘膜重叠的一对源极/漏极区域。

公开(公告)号：US07801309B2

公开(公告)日：2010-09-21

申请号：US11209677

申请日：2005-08-24

申请人： Kazuya Takemoto ,  Tatsuya Usuki

发明人： Kazuya Takemoto ,  Tatsuya Usuki

IPC分类号： H04L9/08 ,  H04L9/00 ,  G06E3/00

CPC分类号： B82Y20/00 ,  B82Y10/00 ,  H04L9/0858 ,  H04L2209/56

摘要： A private key delivery system and a private key delivery method are disclosed. The private key delivery system includes a transmitter, a receiver, and an optical transmission line connecting the transmitter and the receiver. The transmitter includes a single photon generating unit for simultaneously generating two or more single photons having different wavelengths using a quantum dot structure that has quantum dots of various sizes, an optical splitter for splitting the single photons by wavelengths, a phase modulating unit for modulating each of the single photons split by the wavelengths with private key information, and an optical multiplexer for multiplexing the modulated single photons of the different wavelength and for transmitting the multiplexed single photons to the optical transmission line. The multiplexed single photons are received by the receiver, and the private key information is taken out from the received single photons.

摘要翻译： 公开了私钥传送系统和私钥递送方法。 私钥传送系统包括发射机，接收机和连接发射机和接收机的光传输线路。 发射机包括单个光子产生单元，用于使用具有各种尺寸的量子点的量子点结构同时产生具有不同波长的两个或更多个单个光子，用于通过波长分割单个光子的光分路器，用于调制每个光子的相位调制单元 由具有私钥信息的波长分离的单个光子，以及用于复用不同波长的调制单个光子并用于将多路复用单个光子发射到光传输线的光复用器。 复用的单个光子由接收机接收，并且从接收的单个光子中取出私钥信息。

公开(公告)号：US07462539B2

公开(公告)日：2008-12-09

申请号：US11892872

申请日：2007-08-28

申请人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

发明人： Kouji Tsunoda ,  Tatsuya Usuki ,  Masao Taguchi

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/0692 ,  H01L29/7883

摘要： A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

摘要翻译： 半导体器件具有形成在半导体衬底上的隔离区域，并且限定包括选择晶体管区域和直接隧道元件区域的连续有源区域; 形成在所述选择晶体管区域的沟道区上的栅极绝缘膜; 隧道绝缘膜，其形成在所述直接隧道元件区域的部分区域上，并且具有与所述栅极绝缘膜的厚度不同的厚度; 形成在栅极绝缘膜和隧道绝缘膜上方的连续浮栅; 形成在所述浮栅电极的表面上的电极间绝缘膜; 通过所述电极间绝缘膜与所述浮栅相对的控制栅电极; 以及形成在选择晶体管区域的沟道区域的两侧并且不与隧道绝缘膜重叠的一对源极/漏极区域。