公开(公告)号：US07007131B2

公开(公告)日：2006-02-28

申请号：US09752594

申请日：2000-12-27

申请人： Terry L. Kendall ,  Paul D. Ruby

发明人： Terry L. Kendall ,  Paul D. Ruby

IPC分类号： G06F12/00

CPC分类号： G11C29/46 ,  G11C16/3454

摘要： A method wherein a special programming mode of a memory is entered and internal program verification by the memory is disabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. The special programming mode is exited and internal program verification by the memory is enabled. The special programming mode may use hashing to optimize testing for a memory such as a nonvolatile flash memory.

摘要翻译： 一种其中输入存储器的特殊编程模式并且禁止由存储器进行内部程序验证的方法。 还描述了一种具有主机处理器和具有特殊编程模式电路的存储器的装置。 存储器包括用于程序验证的自动化电路。 多个字被编程到存储器中，而没有存储器执行内部程序验证。 退出特殊编程模式，启用内存的内部程序验证。 特殊编程模式可以使用散列来优化诸如非易失性闪存之类的存储器的测试。

公开(公告)号：US08773921B2

公开(公告)日：2014-07-08

申请号：US13572854

申请日：2012-08-13

申请人： Paul D. Ruby ,  Violante Moschiano

发明人： Paul D. Ruby ,  Violante Moschiano

IPC分类号： G11C7/10

CPC分类号： G11C14/0018 ,  G11C16/0483 ,  G11C16/3427

摘要： Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

摘要翻译： 描述了包括存储器阵列中的页缓冲器之间的通信电路的存储器件和方法。 示例包括提供与给定页面缓冲器直接相邻的页面缓冲器的状态信息的通信电路。 交换的信息可以用于调整给定的页面缓冲器以补偿在同时操作的直接相邻数据线中的效果。

公开(公告)号：US20140047302A1

公开(公告)日：2014-02-13

申请号：US13976007

申请日：2011-12-28

申请人： Xin Guo ,  Kiran Pangal ,  Yogesh B. Wakchaure ,  Paul D. Ruby ,  Ravi J. Kumar

发明人： Xin Guo ,  Kiran Pangal ,  Yogesh B. Wakchaure ,  Paul D. Ruby ,  Ravi J. Kumar

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/26 ,  G11C16/3409

摘要： Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.

摘要翻译： 公开了用于对非易失性存储器阵列的存储器单元进行扩展的循环耐久性的示例。 这些示例包括基于程序/擦除循环计数或故障触发来实现一个或多个耐力扩展方案。 一个或多个耐力扩展方案可以包括逐渐读取窗口扩展，逐渐读取窗口移位，擦除空白校验算法，动态软程序或动态预编程。

公开(公告)号：US20130073786A1

公开(公告)日：2013-03-21

申请号：US13234446

申请日：2011-09-16

申请人： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

发明人： Hanmant P. Belgal ,  Ning Wu ,  Paul D. Ruby ,  Andrew Vogan ,  Xin Guo ,  Ivan Kalastirsky ,  Mase J. Taub

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/3422

摘要： Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.

摘要翻译： 描述了用于改善非易失性存储器（NVM）的读取耐久性的装置，系统和方法。 该方法包括：确定对应于NVM块的读取计数; 识别NVM的块是否是部分编程块（PPB）; 当识别出块是PPB时，将读取计数与第一阈值进行比较; 并且当另外标识时，将读取计数与第二阈值进行比较，其中第一阈值小于第二阈值。 该方法还包括：识别作为PPB的块; 确定对应于PPB的未编程页面的第一字线; 以及将所述第一字线发送到所述NVM，其中所述NVM应用：对应于所述PPB的未编程页面的字线的第一读取电压电平和对应于所述PPB的编程页面的字线的第二读取电压电平 PPB。

公开(公告)号：US08472256B2

公开(公告)日：2013-06-25

申请号：US12778838

申请日：2010-05-12

申请人： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

发明人： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

公开(公告)号：US20110280082A1

公开(公告)日：2011-11-17

申请号：US12778838

申请日：2010-05-12

申请人： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

发明人： Paul D. Ruby ,  Violante Moschiano ,  Giovanni Santin

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3459

摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.

摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法包括在编程操作期间将电压施加到与不同组的存储器单元相关联的数据线。 这种方法将电压施加到与已编程其它存储器单元组之后，以与存储器单元的其他组相同的方式编程的最后一组存储器单元相关联的数据线。 描述包括附加存储器件和方法的其它实施例。

公开(公告)号：US20110107014A1

公开(公告)日：2011-05-05

申请号：US12612248

申请日：2009-11-04

申请人： Paul D. Ruby ,  Violante Moschiano

发明人： Paul D. Ruby ,  Violante Moschiano

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C14/0018 ,  G11C16/0483 ,  G11C16/3427

摘要： Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

摘要翻译： 描述了包括存储器阵列中的页缓冲器之间的通信电路的存储器件和方法。 示例包括提供与给定页面缓冲器直接相邻的页面缓冲器的状态信息的通信电路。 交换的信息可以用于调整给定的页面缓冲器以补偿在同时操作的直接相邻数据线中的效果。

公开(公告)号：US06732306B2

公开(公告)日：2004-05-04

申请号：US09749133

申请日：2000-12-26

申请人： Lance W. Dover ,  Robert N. Hasbun ,  Paul D. Ruby ,  William T. Reaves

发明人： Lance W. Dover ,  Robert N. Hasbun ,  Paul D. Ruby ,  William T. Reaves

IPC分类号： G11C2900

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C29/16 ,  G11C29/46 ,  G11C29/50 ,  G11C2029/5002

摘要： A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. Hashing is performed with respect to the plurality of data words to generate a first hash value. The host processor compares the first hash value with a second hash value to see whether the first and second hash values are the same or different. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

摘要翻译： 一种其中输入存储器的特殊编程模式的方法。 特殊编程模式禁用内存的内部验证。 存储器包括用于程序验证的自动化电路。 多个字被编程到存储器中，而没有存储器执行内部程序验证。 对多个数据字执行散列以产生第一散列值。 主机处理器将第一散列值与第二散列值进行比较，以查看第一和第二散列值是相同还是不同。 退出特殊编程模式，启用内存的内部程序验证。 还描述了一种具有主机处理器和具有特殊编程模式电路的存储器的装置。

公开(公告)号：US08510636B2

公开(公告)日：2013-08-13

申请号：US13078226

申请日：2011-04-01

申请人： Paul D. Ruby ,  Hanmant P. Belgal ,  Yogesh B. Wakchaure ,  Xin Guo ,  Scott E. Nelson ,  Svanhild M. Salmons

发明人： Paul D. Ruby ,  Hanmant P. Belgal ,  Yogesh B. Wakchaure ,  Xin Guo ,  Scott E. Nelson ,  Svanhild M. Salmons

IPC分类号： G11C29/00

CPC分类号： H03M13/6325 ,  G06F11/1048 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

摘要： Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level.

摘要翻译： 本发明的实施例描述了用于从非易失性存储器单元读取数据的动态读取参考电压。 在本发明的实施例中，读取的参考电压被校准为使用非易失性存储器件。 本发明的实施例可以包括使用第一读取参考电压电平（例如，初始读取参考电压电平，其值由非易失性器件制造商确定的）从多个非易失性存储器单元读取数据的逻辑和/或模块 ）。 执行错误检查和校正（ECC）算法以识别使用第一读取参考电压电平读取的数据中是否存在错误。 如果识别出读取的数据中的错误，则检索预定值以将第一读取参考电压电平调整到第二读取参考电压电平。

公开(公告)号：US08411508B2

公开(公告)日：2013-04-02

申请号：US12573579

申请日：2009-10-05

申请人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

发明人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

摘要翻译： 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。