公开(公告)号：US12132137B2

公开(公告)日：2024-10-29

申请号：US17881927

申请日：2022-08-05

Applicant: Mellanox Technologies, Ltd.

Inventor： Oren Steinberg ,  Anders Gösta Larsson ,  Attila Fülöp ,  Elad Mentovich ,  Isabelle Cestier ,  Moshe B. Oron

IPC: H01L31/18 ,  H01L31/0304 ,  H01L31/109

CPC classification number: H01L31/1848 ,  H01L31/03048 ,  H01L31/109

Abstract: Processes for continuous compositional grading for realization of low charge carrier barriers in electro-optical heterostructure semiconductor devices are provided. An example process includes forming, onto one or more semiconductor layers of an electro-optical semiconductor device, a first semiconductor layer associated with a first bandgap value and forming, onto the first semiconductor layer, a grading layer associated with a continuous compositional grading. The example method further includes forming, onto the grading layer, a second semiconductor layer associated with a second bandgap value. The second bandgap value is different than the first bandgap value.

公开(公告)号：US12132059B2

公开(公告)日：2024-10-29

申请号：US17722232

申请日：2022-04-15

Applicant: Phion Technologies Corp.

Inventor： Jonathan Nydell ,  Steve Laver

IPC: H04B10/114 ,  G02B19/00 ,  H01L27/144 ,  H01L31/02 ,  H01L31/0224 ,  H01L31/054 ,  H01L31/068 ,  H01L31/075 ,  H01L31/077 ,  H01L31/109 ,  H02J7/00 ,  H02J7/34 ,  H02J50/30 ,  H02J50/40 ,  H02J50/80 ,  H02J50/90 ,  H04B10/112 ,  H04B10/40 ,  H04B10/50 ,  H04B10/61 ,  H04B10/80 ,  H01L25/16 ,  H01L31/0216 ,  H01L31/024 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/0475 ,  H01L31/052

CPC classification number: H01L27/1443 ,  G02B19/0028 ,  G02B19/009 ,  H01L31/02024 ,  H01L31/0224 ,  H01L31/0547 ,  H01L31/0682 ,  H01L31/075 ,  H01L31/077 ,  H01L31/109 ,  H02J7/00032 ,  H02J7/0048 ,  H02J7/345 ,  H02J50/30 ,  H02J50/40 ,  H02J50/80 ,  H02J50/90 ,  H04B10/1123 ,  H04B10/1143 ,  H04B10/40 ,  H04B10/502 ,  H04B10/503 ,  H04B10/61 ,  H04B10/616 ,  H04B10/807 ,  H01L25/167 ,  H01L31/02161 ,  H01L31/02167 ,  H01L31/022441 ,  H01L31/024 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/0352 ,  H01L31/0475 ,  H01L31/052 ,  H02J7/00

Abstract: A method of coordinating wireless power transfer and data communication between a transmitter and a receiver comprising recognizing at the receiver that an energy store electrically coupled to the receiver requires an electrical charge, emitting from the receiver a beacon signal to the transmitter, the beacon signal including information about the receiver and a state of charge of the energy store, recognizing at the receiver first and second localization signals from the transmitter, establishing low-power and high-power laser beam connections between the receiver and the transmitter in response to the localization signals, and communicating further information via the low-power beam on a periodic basis while optical power is being transferred via the high-power beam. The low-power beam connection includes further information about the receiver and the state of charge of the energy store. Optical power is transferred from the transmitter to the receiver via the high-power beam.

公开(公告)号：US20240234611A1

公开(公告)日：2024-07-11

申请号：US18432626

申请日：2024-02-05

Applicant: SolAero Technologies Corp.

Inventor： Arthur Cornfeld ,  Jeff Stainfeldt

IPC: H01L31/0725 ,  H01L31/0304 ,  H01L31/048 ,  H01L31/0687 ,  H01L31/18

CPC classification number: H01L31/0725 ,  H01L31/0304 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/048 ,  H01L31/06875 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1848 ,  H01L31/1856 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/50

Abstract: A solar cell fabricated from a semiconductor growth substrate; that is sub sequentially removed a sequence of layers of semiconductor material grown on the semiconductor growth substrate forming the solar cell; a metal contact layer deposited over the sequence of layers; of a permanent supporting substrate being affixed directly over the metal contact layer and permanently bonded thereto.

公开(公告)号：US20240113251A1

公开(公告)日：2024-04-04

申请号：US18519778

申请日：2023-11-27

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L31/0224 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/109 ,  H01L33/02 ,  H01L33/04 ,  H01L33/14 ,  H01L33/32

CPC classification number: H01L33/002 ,  H01L31/022408 ,  H01L31/03048 ,  H01L31/0352 ,  H01L31/035236 ,  H01L31/105 ,  H01L31/109 ,  H01L33/0025 ,  H01L33/025 ,  H01L33/04 ,  H01L33/14 ,  H01L33/145 ,  H01L33/32 ,  H01L33/06 ,  H01L2933/0008

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.

公开(公告)号：US20190189826A1

公开(公告)日：2019-06-20

申请号：US16282762

申请日：2019-02-22

Applicant: SOLAR JUNCTION CORPORATION

Inventor： FERRAN SUAREZ ,  TING LIU ,  HOMAN B. YUEN ,  DAVID TANER BILIR ,  ARSEN SUKIASYAN ,  JORDAN LANG

IPC: H01L31/0725 ,  H01L31/0687 ,  H01L31/0735 ,  H01L31/0304

CPC classification number: H01L31/0725 ,  H01L31/03048 ,  H01L31/0687 ,  H01L31/0735 ,  Y02E10/544

Abstract: Multijunction photovoltaic cells having at least three subcells are disclosed, in which at least one of the subcells comprises a base layer formed of GaInNAsSb. The GaInNAsSb subcells exhibit high internal quantum efficiencies over a broad range of irradiance energies.

公开(公告)号：US20190035968A1

公开(公告)日：2019-01-31

申请号：US16145947

申请日：2018-09-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Alexander Dobrinsky ,  Michael Shur

IPC: H01L33/00 ,  H01L31/0352 ,  H01L31/0224 ,  H01L31/0304 ,  H01L33/40 ,  H01L33/32 ,  H01L33/08 ,  H01L33/06 ,  H01L31/109

CPC classification number: H01L33/0025 ,  H01L31/022408 ,  H01L31/03048 ,  H01L31/035227 ,  H01L31/035236 ,  H01L31/035272 ,  H01L31/109 ,  H01L33/025 ,  H01L33/04 ,  H01L33/06 ,  H01L33/08 ,  H01L33/18 ,  H01L33/32 ,  H01L33/405

Abstract: A semiconductor heterostructure including a polarization doped region is described. The region can correspond to an active region of a device, such as an optoelectronic device. The region includes an n-type semiconductor side and a p-type semiconductor side and can include one or more quantum wells located there between. The n-type and/or p-type semiconductor side can be formed of a group III nitride including aluminum and indium, where a first molar fraction of aluminum nitride and a first molar fraction of indium nitride increase (for the n-type side) or decrease (for the p-type side) along a growth direction to create the n- and/or p-polarizations.

公开(公告)号：US20180323345A1

公开(公告)日：2018-11-08

申请号：US16025186

申请日：2018-07-02

Applicant: Sensor Electronic Technology, Inc.

Inventor： Alexander Dobrinsky ,  Maxim S. Shatalov ,  Mikhail Gaevski ,  Michael Shur

IPC: H01L33/38 ,  H01L33/06 ,  H01L33/12 ,  H01L33/14 ,  H01L33/22 ,  H01L33/32 ,  H01L33/40 ,  H01L33/46 ,  H01L33/00 ,  H01L31/0352 ,  H01L31/0236 ,  H01L31/0304 ,  H01L31/0224 ,  H01L31/0232 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L33/387 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/02363 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/1848 ,  H01L31/1852 ,  H01L31/1864 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/145 ,  H01L33/20 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L33/405 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0091

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.

公开(公告)号：US10062813B2

公开(公告)日：2018-08-28

申请号：US15306441

申请日：2015-04-24

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Siegfried Herrmann ,  Matthias Sperl

IPC: H01L33/48 ,  F21V8/00 ,  H01L33/58 ,  H01L33/60 ,  H01L27/02 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0232 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18 ,  H01L33/00 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/50 ,  H01L33/62

CPC classification number: H01L33/486 ,  G02B6/0006 ,  G02B6/0028 ,  G02B6/0073 ,  H01L27/0248 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02322 ,  H01L31/02327 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/186 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/502 ,  H01L33/58 ,  H01L33/60 ,  H01L33/62 ,  H01L2924/181 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2933/0091

Abstract: An optoelectronic component (100) comprises an optoelectronic semiconductor chip (10), a first contact area (31) and a second contact area (32), which is laterally offset with respect to the first contact area and is electrically insulated therefrom, and a housing element (40). The first contact area (31) is electrically conductively connected to the first semiconductor layer (21) and the second contact area (32) is electrically conductively connected to the second semiconductor layer (22) of the optoelectronic semiconductor chip. The first contact area (31) and the second contact area (32) project beyond the optoelectronic semiconductor chip laterally in each case. The housing element (40) is fixed to the first contact area (31) and the second contact area (32) in regions in which the first contact area (31) and the second contact area (32) project beyond the optoelectronic semiconductor chip laterally in each case. The housing element surrounds the optoelectronic semiconductor chip at least partly. A surface of the housing element that faces the optoelectronic semiconductor chip is embodied as reflective at least in partial regions. A wall of the housing element has a cutout (61).

公开(公告)号：US20180172903A1

公开(公告)日：2018-06-21

申请号：US15837173

申请日：2017-12-11

Applicant: Massachusetts Institute of Technology ,  National University of Singapore ,  Nanyang Technological University

Inventor： Wenjia Zhang ,  Bing Wang ,  Li Zhang ,  Zhaomin Zhu ,  Jurgen Michel ,  Soo-Jin Chua ,  Li-Shiuan Peh ,  Siau Ben Chiah ,  Eng Kian Kenneth Lee

IPC: G02B6/12 ,  H01L33/32 ,  H01L33/06 ,  H01L33/12 ,  G02B6/42 ,  H01L31/153 ,  H01L31/12 ,  H01L31/0392 ,  H01L31/0352 ,  H01L31/0304 ,  H01L27/15 ,  H01L27/06 ,  H01L21/8258 ,  H01L33/00

CPC classification number: G02B6/12004 ,  G02B6/00 ,  G02B6/12 ,  G02B6/428 ,  G02B2006/121 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/15 ,  H01L31/02327 ,  H01L31/03044 ,  H01L31/03048 ,  H01L31/035236 ,  H01L31/035281 ,  H01L31/0392 ,  H01L31/105 ,  H01L31/12 ,  H01L31/125 ,  H01L31/153 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  Y02E10/544

Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.

公开(公告)号：US20180069154A1

公开(公告)日：2018-03-08

申请号：US15798909

申请日：2017-10-31

Applicant: Sensor Electronic Technology, Inc.

Inventor： Alexander Dobrinsky ,  Maxim S. Shatalov ,  Mikhail Gaevski ,  Michael Shur

IPC: H01L33/40 ,  H01L33/20 ,  H01L33/44 ,  H01L33/02 ,  H01L33/00

CPC classification number: H01L33/405 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03048 ,  H01L31/1848 ,  H01L31/1852 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/025 ,  H01L33/12 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/387 ,  H01L33/44 ,  H01L33/46 ,  H01L2933/0016 ,  H01L2933/0091

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. An n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second metallic contact layer can be located over a second portion of the n-type contact region, where the second metallic contact layer is formed of a reflective metallic material.