公开(公告)号：US20220223429A1

公开(公告)日：2022-07-14

申请号：US17352139

申请日：2021-06-18

Applicant: The Regents of the University of California

Inventor： Brian Romanczyk ,  Emmanuel Kayede ,  Wenjian Liu ,  Islam Sayed ,  Umesh K. Mishra

IPC: H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  H01L29/872 ,  H01L21/285 ,  H01L21/308 ,  H01L29/66 ,  H01L29/34

Abstract: N-polar transistor structures have relied on the use of dry etch processes that use plasmas generated from gaseous species to remove III-N layers as commercially viable wet etchants do not exist. The present disclosure reports on methods for the fabrication of N-polar III-N transistors using wet etches along with transistor structures that are enabled by the availability of wet-etches.

公开(公告)号：US08796912B2

公开(公告)日：2014-08-05

申请号：US13622979

申请日：2012-09-19

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistances with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

公开(公告)号：US09691712B2

公开(公告)日：2017-06-27

申请号：US14466420

申请日：2014-08-22

Applicant: The Regents of the University of California

Inventor： Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  C30B25/02 ,  C30B29/40 ,  H01L33/00 ,  H01L33/12 ,  H01L33/32

CPC classification number: H01L23/562 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

公开(公告)号：US09263423B2

公开(公告)日：2016-02-16

申请号：US14730010

申请日：2015-06-03

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62 ,  H01L27/15 ,  H01L33/62 ,  H01L25/075 ,  H01L33/48 ,  H01L33/42 ,  H01L33/64 ,  H01L33/38 ,  H01L33/20

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

公开(公告)号：US20150294960A1

公开(公告)日：2015-10-15

申请号：US14730010

申请日：2015-06-03

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01L25/075 ,  H01L33/48 ,  H01L33/20 ,  H01L33/64 ,  H01L33/38 ,  H01L33/62 ,  H01L33/42

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了一种排列成阵列的多个交错像素，具有非常低的串联电阻，并具有改善的电流扩散和改善的散热。每个像素是具有尺寸l侧面的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US09076711B2

公开(公告)日：2015-07-07

申请号：US14553625

申请日：2014-11-25

Applicant: The Regents of the University of California

Inventor： Arpan Chakraborty ,  Likun Shen ,  Umesh K. Mishra

IPC: H01J1/62 ,  H01L27/15 ,  H01L33/62

CPC classification number: H01L25/0753 ,  F21K9/00 ,  H01L27/156 ,  H01L33/08 ,  H01L33/14 ,  H01L33/20 ,  H01L33/38 ,  H01L33/385 ,  H01L33/42 ,  H01L33/486 ,  H01L33/62 ,  H01L33/64 ,  H01L2924/0002 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2924/00

Abstract: The present invention discloses a plurality of interdigitated pixels arranged in an array, having a very low series-resistance with improved current spreading and improved heat-sinking. Each pixel is a square with sides of dimension l. The series resistance is minimized by increasing the perimeter of an active region for the pixels. The series resistance is also minimized by shrinking the space between a mesa and n-contact for each pixel.

Abstract translation: 本发明公开了排列成阵列的多个叉指像素，具有非常低的串联电阻，具有改进的电流扩散和改善的散热。 每个像素是具有尺寸l的边的正方形。 通过增加像素的有源区域的周长来使串联电阻最小化。 串联电阻也通过缩小每个像素的台面和n接触之间的空间来最小化。

公开(公告)号：US20150137137A1

公开(公告)日：2015-05-21

申请号：US14566443

申请日：2014-12-10

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Srabanti Chowdhury ,  Ramya Yeluri ,  Christophe Hurni ,  Umesh K. Mishra ,  Ilan Ben-Yaacov

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/0646 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/861

Abstract: A current aperture vertical electron transistor (CAVET) with ammonia (NH3) based molecular beam epitaxy (MBE) grown p-type Gallium Nitride (p-GaN) as a current blocking layer (CBL). Specifically, the CAVET features an active buried Magnesium (Mg) doped GaN layer for current blocking purposes. This structure is very advantageous for high power switching applications and for any device that requires a buried active p-GaN layer for its functionality.

Abstract translation: 具有基于氨（NH3）的分子束外延（MBE）的电流孔径垂直电子晶体管（CAVET）生长的p型氮化镓（p-GaN）作为电流阻挡层（CBL）。 具体来说，CAVET具有用于电流阻塞目的的有源掩埋的镁（Mg）掺杂的GaN层。 这种结构对于大功率开关应用以及需要掩埋有源p-GaN层用于其功能的任何器件是非常有利的。

公开(公告)号：US12211955B2

公开(公告)日：2025-01-28

申请号：US17576716

申请日：2022-01-14

Applicant: The Regents of the University of California

Inventor： Kamruzzaman Khan ,  Elaheh Ahmadi ,  Stacia Keller ,  Christian Wurm ,  Umesh K. Mishra

IPC: H01L33/32 ,  H01L33/00

Abstract: A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

公开(公告)号：US12159929B1

公开(公告)日：2024-12-03

申请号：US17114307

申请日：2020-12-07

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: An electronic device including a substrate a group III-V layer on or above the substrate, wherein the III-V layer has an in-plane lattice constant that is greater than that of gallium nitride or wherein the III-V layer is at least partially relaxed; and an active region including a coherently strained group III-V channel layer on or above the III-V layer; wherein electron mobility in the channel layer is increased by the strain. Structures with an in-plane lattice constant that is smaller than that of gallium nitride are used for increasing the hole mobility by strain.

公开(公告)号：US20240063340A1

公开(公告)日：2024-02-22

申请号：US17642057

申请日：2020-09-10

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Umesh K. Mishra ,  Shubhra Pasayat ,  Chirag Gupta

IPC: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/075 ,  H01L33/20

CPC classification number: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/0753 ,  H01L33/20

Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.