公开(公告)号：US08883600B1

公开(公告)日：2014-11-11

申请号：US13725152

申请日：2012-12-21

申请人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

发明人： Scott E. Thompson ,  Lucian Shifren ,  Pushkar Ranade ,  Yujie Liu ,  Sung Hwan Kim ,  Lingquan Wang ,  Dalong Zhao ,  Teymur Bakhishev ,  Thomas Hoffmann ,  Sameer Pradhan ,  Michael Duane

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7836

摘要： A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

摘要翻译： 晶体管及其制造方法包括至少部分地形成在沟道层和栅极堆叠下方的半导体衬底中的屏蔽层，栅极堆叠包括在栅极叠层的任一侧上的间隔结构。 晶体管包括沟道层中的浅掺杂稀土漏极区和相对于屏蔽层底部的深度处的深掺杂漏极区，用于减少结漏电流。 还可以包括补偿层以防止背栅控制的损失。

公开(公告)号：US09406567B1

公开(公告)日：2016-08-02

申请号：US13407527

申请日：2012-02-28

申请人： Lucian Shifren ,  Pushkar Ranade ,  Thomas Hoffmann ,  Scott E. Thompson

发明人： Lucian Shifren ,  Pushkar Ranade ,  Thomas Hoffmann ,  Scott E. Thompson

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823892

摘要： Fabrication of a first device on a substrate is performed by exposing a first device region, removing a portion of the substrate to create a trench in the first device region, forming a screen layer with a first dopant concentration in the trench on the substrate, and forming an epitaxial channel on the screen layer having a first thickness. On or more other devices are similarly formed on the substrate independent of each other with epitaxial channels of different thicknesses than the first thickness. Devices with screen layers having the same dopant concentration but with different epitaxial channel thicknesses have different threshold voltages. Thus, a wide variety of threshold voltage devices can be formed on the same substrate. Further threshold voltage setting can be achieved through variations in the dopant concentration of the screen layers.

摘要翻译： 通过暴露第一器件区域，去除衬底的一部分以在第一器件区域中形成沟槽，在衬底上的沟槽中形成具有第一掺杂剂浓度的屏蔽层，从而在衬底上制造第一器件，以及 在具有第一厚度的屏幕层上形成外延沟道。 在衬底上类似地形成一个或多个其它器件，彼此独立地具有不同于第一厚度的厚度的外延沟道。 具有相同掺杂浓度但具有不同外延沟道厚度的屏幕层的器件具有不同的阈值电压。 因此，可以在同一衬底上形成各种阈值电压器件。 可以通过屏幕层的掺杂剂浓度的变化来实现进一步的阈值电压设定。

公开(公告)号：US08735987B1

公开(公告)日：2014-05-27

申请号：US13489824

申请日：2012-06-06

申请人： Thomas Hoffmann ,  Scott E. Thompson ,  Pushkar Ranade

发明人： Thomas Hoffmann ,  Scott E. Thompson ,  Pushkar Ranade

IPC分类号： H01L27/092

CPC分类号： H01L27/1108 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4958 ,  H01L29/4966

摘要： A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

摘要翻译： 半导体器件包括具有在其中形成有第一有源区和第二有源区的半导体表面的衬底，其中第一有源区由表面处的基本上未掺杂的层和在第一有源区下面的第一导电类型的高掺杂屏蔽层 第一基本上未掺杂的层，并且第二有源区由表面处的第二基本上未掺杂的层和在第二基本未掺杂的层下面的第二导电类型的第二高掺杂屏蔽层组成。 该半导体器件还包括形成在每个第一有源区中的栅极堆叠，而第二有源区由至少一个栅极电介质层和金属层组成，其中金属具有相对于 半导体表面。

公开(公告)号：US08614128B1

公开(公告)日：2013-12-24

申请号：US13591767

申请日：2012-08-22

申请人： Scott E. Thompson ,  Thomas Hoffmann ,  Lance Scudder ,  U. C. Sridharan ,  Dalong Zhao ,  Pushkar Ranade ,  Michael Duane ,  Paul E. Gregory

发明人： Scott E. Thompson ,  Thomas Hoffmann ,  Lance Scudder ,  U. C. Sridharan ,  Dalong Zhao ,  Pushkar Ranade ,  Michael Duane ,  Paul E. Gregory

IPC分类号： H01L21/8234

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11 ,  H01L29/0653 ,  H01L29/16

摘要： Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

摘要翻译： 提供了制造半导体器件及其器件的方法。 一种方法包括提供具有第一和第二层的具有半导体表面的衬底，其中半导体表面具有包括第一和第二有源区的多个有源区。 在第一有源区中，第一层是未掺杂层，第二层是高度掺杂的掩膜层。 该方法还包括移除第一层的一部分以减少第一有源区的至少一部分的基本上未掺杂层的厚度，而在第二有源区中没有相应的第一层的厚度减小。 该方法还包括在多个有源区域中形成半导体器件。 在该方法中，基于第一有源区的部分中的衬底所需的阈值电压调整来选择去除第一层的部分。

公开(公告)号：US08629016B1

公开(公告)日：2014-01-14

申请号：US13459971

申请日：2012-04-30

申请人： Thomas Hoffmann ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson

发明人： Thomas Hoffmann ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson

IPC分类号： H01L21/8238

CPC分类号： H01L21/22 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66477 ,  H01L29/78

摘要： Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.

摘要翻译： 通过从掺杂底层的差分向外扩散，在公共外延层中形成多晶体管类型。 差分外扩散影响FET沟道的厚度，FET沟道中的掺杂浓度以及栅介质层与掺杂底层之间的距离。 差分外扩散可以通过差分施加掺杂剂迁移抑制剂如碳来实现; 用具有相同导电类型但不同扩散性的两种或更多种掺杂剂差异掺杂底层; 和/或差异地施加热能。

公开(公告)号：US20130181298A1

公开(公告)日：2013-07-18

申请号：US13787073

申请日：2013-03-06

申请人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：US08421162B2

公开(公告)日：2013-04-16

申请号：US12895813

申请日：2010-09-30

申请人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

发明人： Lucian Shifren ,  Pushkar Ranade ,  Paul E. Gregory ,  Sachin R. Sonkusale ,  Weimin Zhang ,  Scott E. Thompson

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7836

摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。

公开(公告)号：US20110248352A1

公开(公告)日：2011-10-13

申请号：US12971884

申请日：2010-12-17

申请人： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson ,  Sachin R. Sonkusale ,  Weimin Zhang

发明人： Lucian Shifren ,  Pushkar Ranade ,  Scott E. Thompson ,  Sachin R. Sonkusale ,  Weimin Zhang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/7833

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。

公开(公告)号：US08796048B1

公开(公告)日：2014-08-05

申请号：US13469598

申请日：2012-05-11

申请人： Scott E. Thompson ,  Pushkar Ranade ,  Lance Scudder ,  Charles Stager

发明人： Scott E. Thompson ,  Pushkar Ranade ,  Lance Scudder ,  Charles Stager

IPC分类号： H01L21/66 ,  H01L21/67 ,  H01L21/762

CPC分类号： H01L21/67253 ,  H01L21/76229 ,  H01L22/12 ,  H01L22/30

摘要： The present disclosure provides methods and structures for measurement, control, and monitoring the thickness of thin film layers formed as part of a semiconductor manufacturing process. The methods and structures presented provide the capability to measure and monitor the thickness of the thin film using trench line structures. In certain embodiments, the thin film thickness measurement system can be integrated with thin film growth and control software, providing automated process control (APC) or statistical process control (SPC) capability by measuring and monitoring the thin film thickness during manufacturing. Methods for measuring the thickness of thin films can be important to the fabrication of integrated circuits because the thickness and uniformity of the thin film can determine electrical characteristics of the transistors being fabricated.

摘要翻译： 本公开提供了用于测量，控制和监测作为半导体制造工艺的一部分形成的薄膜层的厚度的方法和结构。 所提出的方法和结构提供了使用沟槽结构测量和监测薄膜的厚度的能力。 在某些实施例中，薄膜厚度测量系统可以与薄膜生长和控制软件集成，通过在制造期间测量和监测薄膜厚度来提供自动化过程控制（APC）或统计过程控制（SPC）能力。 用于测量薄膜厚度的方法对于集成电路的制造而言是重要的，因为薄膜的厚度和均匀性可以确定正在制造的晶体管的电特性。

公开(公告)号：US08759872B2

公开(公告)日：2014-06-24

申请号：US12971955

申请日：2010-12-17

申请人： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

发明人： Reza Arghavani ,  Pushkar Ranade ,  Lucian Shifren ,  Scott E. Thompson ,  Catherine de Villeneuve

IPC分类号： H01L21/336 ,  H01L21/338

CPC分类号： H01L27/0921 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/365 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7836

摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD, so that the body bias can be tuned separately from VT for a given device.

摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。 指示特征性缺口的新型掺杂物分布使得能够在精确范围内调整VT设置。 可以通过适当选择金属来扩展该VT设定范围，使得在管芯上容纳非常宽范围的VT设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 结果是能够独立地控制VT（具有低电平（VT））和VDD（VDD），从而使给定器件的体偏压可以与VT分开调谐。