CMOS gate stack structures and processes
    2.
    发明授权
    CMOS gate stack structures and processes 有权
    CMOS栅极堆叠结构和工艺

    公开(公告)号:US08735987B1

    公开(公告)日:2014-05-27

    申请号:US13489824

    申请日:2012-06-06

    IPC分类号: H01L27/092

    摘要: A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

    摘要翻译: 半导体器件包括具有在其中形成有第一有源区和第二有源区的半导体表面的衬底,其中第一有源区由表面处的基本上未掺杂的层和在第一有源区下面的第一导电类型的高掺杂屏蔽层 第一基本上未掺杂的层,并且第二有源区由表面处的第二基本上未掺杂的层和在第二基本未掺杂的层下面的第二导电类型的第二高掺杂屏蔽层组成。 该半导体器件还包括形成在每个第一有源区中的栅极堆叠,而第二有源区由至少一个栅极电介质层和金属层组成,其中金属具有相对于 半导体表面。

    CMOS structures and processes based on selective thinning
    3.
    发明授权
    CMOS structures and processes based on selective thinning 有权
    基于选择性稀化的CMOS结构和工艺

    公开(公告)号:US08614128B1

    公开(公告)日:2013-12-24

    申请号:US13591767

    申请日:2012-08-22

    IPC分类号: H01L21/8234

    摘要: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

    摘要翻译: 提供了制造半导体器件及其器件的方法。 一种方法包括提供具有第一和第二层的具有半导体表面的衬底,其中半导体表面具有包括第一和第二有源区的多个有源区。 在第一有源区中,第一层是未掺杂层,第二层是高度掺杂的掩膜层。 该方法还包括移除第一层的一部分以减少第一有源区的至少一部分的基本上未掺杂层的厚度,而在第二有源区中没有相应的第一层的厚度减小。 该方法还包括在多个有源区域中形成半导体器件。 在该方法中,基于第一有源区的部分中的衬底所需的阈值电压调整来选择去除第一层的部分。

    Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
    4.
    发明授权
    Method for fabricating multiple transistor devices on a substrate with varying threshold voltages 有权
    在具有不同阈值电压的衬底上制造多个晶体管器件的方法

    公开(公告)号:US09406567B1

    公开(公告)日:2016-08-02

    申请号:US13407527

    申请日:2012-02-28

    IPC分类号: H01L21/8238 H01L21/8234

    摘要: Fabrication of a first device on a substrate is performed by exposing a first device region, removing a portion of the substrate to create a trench in the first device region, forming a screen layer with a first dopant concentration in the trench on the substrate, and forming an epitaxial channel on the screen layer having a first thickness. On or more other devices are similarly formed on the substrate independent of each other with epitaxial channels of different thicknesses than the first thickness. Devices with screen layers having the same dopant concentration but with different epitaxial channel thicknesses have different threshold voltages. Thus, a wide variety of threshold voltage devices can be formed on the same substrate. Further threshold voltage setting can be achieved through variations in the dopant concentration of the screen layers.

    摘要翻译: 通过暴露第一器件区域,去除衬底的一部分以在第一器件区域中形成沟槽,在衬底上的沟槽中形成具有第一掺杂剂浓度的屏蔽层,从而在衬底上制造第一器件,以及 在具有第一厚度的屏幕层上形成外延沟道。 在衬底上类似地形成一个或多个其它器件,彼此独立地具有不同于第一厚度的厚度的外延沟道。 具有相同掺杂浓度但具有不同外延沟道厚度的屏幕层的器件具有不同的阈值电压。 因此,可以在同一衬底上形成各种阈值电压器件。 可以通过屏幕层的掺杂剂浓度的变化来实现进一步的阈值电压设定。

    Architectural design for manual invoicing application software
    9.
    发明授权
    Architectural design for manual invoicing application software 有权
    手工发票应用软件的建筑设计

    公开(公告)号:US08321308B2

    公开(公告)日:2012-11-27

    申请号:US12327354

    申请日:2008-12-03

    IPC分类号: G07B17/00

    摘要: Methods, systems, and apparatus, including computer program products, for implementing a software architecture design for a software application implementing manual invoicing. The application is structured as multiple process components interacting with each other through service interfaces, and multiple service operations, each being implemented for a respective process component. The process components include a Customer Invoice Processing process component, a Due Item Processing process component, a Payment Processing process component, an Accounting process component, a Project Processing process component, and a Balance of Foreign Payment Management process component.

    摘要翻译: 方法,系统和装置,包括计算机程序产品,用于实施用于实施手动发票的软件应用的软件架构设计。 应用程序被构造为通过服务接口彼此交互的多个进程组件,以及针对相应进程组件实现的多个服务操作。 过程组件包括客户发票处理过程组件,到期项目处理过程组件,支付处理过程组件,会计过程组件,项目处理过程组件和外部支付管理平衡流程组件。